Altera
參數(shù)資料
型號(hào): EP1K100QI208-2N
廠商: Altera
文件頁(yè)數(shù): 34/86頁(yè)
文件大?。?/td> 0K
描述: IC ACEX 1K FPGA 100K 208-PQFP
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝: 144
系列: ACEX-1K®
LAB/CLB數(shù): 624
邏輯元件/單元數(shù): 4992
RAM 位總計(jì): 49152
輸入/輸出數(shù): 147
門數(shù): 257000
電源電壓: 2.375 V ~ 2.625 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 208-BFQFP
供應(yīng)商設(shè)備封裝: 208-PQFP(28x28)
其它名稱: 544-1826
EP1K100QI208-2N-ND
4
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
General
Description
Altera ACEX 1K devices provide a die-efficient, low-cost architecture by
combining look-up table (LUT) architecture with EABs. LUT-based logic
provides optimized performance and efficiency for data-path, register
intensive, mathematical, or digital signal processing (DSP) designs, while
EABs implement RAM, ROM, dual-port RAM, or first-in first-out (FIFO)
functions. These elements make ACEX 1K suitable for complex logic
functions and memory functions such as digital signal processing, wide
data-path manipulation, data transformation and microcontrollers, as
required in high-performance communications applications. Based on
reconfigurable CMOS SRAM elements, the ACEX 1K architecture
incorporates all features necessary to implement common gate array
megafunctions, along with a high pin count to enable an effective interface
with system components. The advanced process and the low voltage
requirement of the 2.5-V core allow ACEX 1K devices to meet the
requirements of low-cost, high-volume applications ranging from DSL
modems to low-cost switches.
The ability to reconfigure ACEX 1K devices enables complete testing prior
to shipment and allows the designer to focus on simulation and design
verification. ACEX 1K device reconfigurability eliminates inventory
management for gate array designs and test vector generation for fault
coverage.
Table 4 shows ACEX 1K device performance for some common designs.
All performance results were obtained with Synopsys DesignWare or
LPM functions. Special design techniques are not required to implement
the applications; the designer simply infers or instantiates a function in a
Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or
schematic design file.
Notes:
(1)
This application uses combinatorial inputs and outputs.
(2)
This application uses registered inputs and outputs.
Table 4. ACEX 1K Device Performance
Application
Resources
Used
Performance
LEs
EABs
Speed Grade
Units
-1
-2
-3
16-bit loadable counter
16
0
285
232
185
MHz
16-bit accumulator
16
0
285
232
185
MHz
16-to-1 multiplexer (1)
10
0
3.5
4.5
6.6
ns
16-bit multiplier with 3-stage pipeline(2)
592
0
156
131
93
MHz
256
× 16 RAM read cycle speed (2)
0
1
278
196
143
MHz
256
× 16 RAM write cycle speed (2)
0
1
185
143
111
MHz
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