參數(shù)資料
型號(hào): EMC2103-2-AP-TR
廠商: STANDARD MICROSYSTEMS CORP
元件分類: 模擬信號(hào)調(diào)理
中文描述: SPECIALTY ANALOG CIRCUIT, QCC16
封裝: 4 X 4 MM, ROHS COMPLIANT, QFN-16
文件頁(yè)數(shù): 66/89頁(yè)
文件大?。?/td> 1243K
代理商: EMC2103-2-AP-TR
RPM-Based Fan Controller with HW Thermal Shutdown
Datasheet
SMSC EMC2103
69
Revision 0.90 (08-19-08)
DATASHEET
6.34
GPIO Direction Register (EMC2103-2 Only)
The GPIO Direction Register controls the direction of GPIOs 1 and 2.
Bit 1 - GPIO2_DIR - Determines the direction of GPIO2.
‘0’ (default) - GPIO2 is configured as an input.
‘1’ - GPIO1 is configured as an output.
Bit 0 - GPIO2_DIR - Determines the direction of GPIO1.
‘0’ (default) - GPIO1 is configured as an input.
‘1’ - GPIO1 is configured as an output.
6.35
GPIO Output Configuration Register (EMC2103-2 Only)
The GPIO Output Configuration Register controls the output pin type of each GPIO pin.
Bit 1 - GPIO2_OT - Determines the output type for GPIO2.
‘0’ (default) - GPIO2 is configured as an open drain output (if enabled as an output).
‘1’ - GPIO2 is configured as a push-pull output (if enabled as an output).
Bit 0 - GPIO1_OT - Determines the output type for GPIO1.
‘0’ (default) - GPIO1 is configured as an open drain output (if enabled as an output).
‘1’ - GPIO1 is configured as a push-pull output (if enabled as an output).
6.36
GPIO Input Register (EMC2103-2 Only)
The GPIO Input Register indicates the state of the corresponding GPIO pin. When a GPIO is
configured as an input, any change of state will assert the ALERT# pin (unless GPIO interrupts are
masked, see Section 6.15).
Table 6.51 GPIO Direction Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
E1h
R/W
GPIO
Direction 1
--
GPIO
2_DIR
GPIO
1_DIR
00h
Table 6.52 GPIO Output Configuration Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
E2
R/W
GPIO
Output
Config
-
GPIO
2_OT
GPIO
1_OT
00h
Table 6.53 GPIO Input Register
ADDR
R/W
REGISTER
B7B6B5B4B3B2
B1
B0
DEFAULT
E3h
R
GPIO Input
-
GPIO
2_IN
GPIO
1_IN
00h
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