參數(shù)資料
型號(hào)： EMC2103-2-AP-TR
廠商： STANDARD MICROSYSTEMS CORP
元件分類： 模擬信號(hào)調(diào)理
中文描述： SPECIALTY ANALOG CIRCUIT, QCC16
封裝： 4 X 4 MM, ROHS COMPLIANT, QFN-16
文件頁數(shù)： 46/89頁
文件大小： 1243K
代理商： EMC2103-2-AP-TR
RPM-Based Fan Controller with HW Thermal Shutdown
Datasheet
Revision 0.90 (08-19-08)
50
SMSC EMC2103
DATASHEET
The REC Configuration Register determines whether Resistance Error Correction is used for each
external diode channel.
Bit 2 - REC3 (EMC2102-2 only)- Controls the Resistance Error Correction functionality of External
Diode 3 (if enabled)
‘0’ - the REC functionality for External Diode 3 is disabled
‘1’ (default) - the REC functionality for External Diode 3 is enabled.
Bit 1 - REC2 (EMC2103-2 only)- Controls the Resistance Error Correction functionality of External
Diode 2. If External Diode 2 is selected as the hardware shutdown channel then this bit is read only
and determined by the SHDN_SEL pin (see Section 5.1.1).
‘0’ - the REC functionality for External Diode 2 is disabled
‘1’ - the REC functionality for External Diode 2 is enabled.
Bit 0 - REC1 - Indicates the Resistance Error Correction functionality of External Diode 1. If External
Diode 1 is selected as the hardware shutdown channel then this bit is read only and determined by
the SHDN_SEL pin (see Section 5.1.1).
‘0’ - the REC functionality for External Diode 1 is disabled
‘1’ - the REC functionality for External Diode 1 is enabled.
The REC Configuration Register is software locked.
6.9
Critical Temperature Limit Registers
The Critical Temperature Limit Registers store the Critical Temperature Limit. At power up, none of the
respective channels are linked to the SYS_SHDN pin or the Hardware set Thermal/Critical Shutdown
circuitry.
Whenever one of the registers is updated, two things occur. First, the register is locked so that it cannot
be updated again without a power on reset. Second, the respective temperature channel is linked to
the SYS_SHDN pin and the Hardware set Thermal/Critical Shutdown Circuitry. At this point, if the
measured temperature channel exceeds the Critical limit, the SYS_SHDN pin will be asserted, the
appropriate bit set in the Tcrit Status Register, and the TCRIT bit in the Interrupt Status Register will
be set.
Table 6.14 Limit Registers
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
19h
R/W
once
External Diode
1 Tcrit Limit
Sign
64
32
16
8
4
2
1
64h
(+100°C)
1Ah
R/W
once
External Diode
2 Tcrit Limit
Sign
64
32
16
8
4
2
1
64h
(+100°C)
1Bh
R/W
once
External Diode
3 Tcrit Limit
Sign
64
32
16
8
4
2
1
64h
(+100°C)
1Dh
R/W
once
Internal Diode
Tcrit Limit
Sign
64
32
16
8
4
2
1
64h
(+100°C)
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