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參數(shù)資料
| 型號： | ELANSC400-33AC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Single-Chip, Low-Power, PC/AT-Compatible Microcontrollers |
| 中文描述： | 32-BIT, FLASH, 33 MHz, MICROCONTROLLER, PBGA292 |
| 封裝： | PLASTIC, BGA-292 |
| 文件頁數(shù)： | 15/132頁 |
| 文件大?。?/td> | 2400K |
| 代理商： | ELANSC400-33AC |
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élanSC400 and élanSC410 Microcontrollers Data Sheet
15
ROM/Flash Memory Interface
The integrated ROM/Flash memory interface supports
the following features:
I
8-, 16-, and 32-bit ROM/Flash memory interfaces
I
Three ROM/Flash memory chip selects
I
Burst-mode ROMs
I
ROM accesses at both ISA and CPU speeds
(normal and fast-speed modes)
I
Dedicated ROM Read and ROM Write signals for
better performance
Each ROM space can accommodate up to 64 Mbyte of
ROM. The three ROM spaces can be individually write-
protected. This is useful for protecting code residing in
Flash memory devices.
Two of the three ROM/Flash memory chip selects can
be remapped to a PC Card socket via pinstrap or soft-
ware control. This feature supports reprogramming of
soldered-down Flash memory boot devices and also
simplifies testing of BIOS/XIP OS code.
Three ROM access modes are supported: Normal
mode, Fast mode, and Burst mode. A different set of
timings is used in each mode. In Normal ROM access
mode, the bus cycles follow ISA-like timings. In Fast
ROM access mode, the bus cycle timing occurs at the
CPU clock rate with controls for wait-state insertion.
Burst ROM access timing is used when the ROM/Flash
memory interface is fulfilling an internal CPU burst re-
quest to support a cache line refill.
Wait states are supported for all ROM and Flash mem-
ory accesses, including Burst mode. Burst-mode
(page-mode) ROM reads are supported for either a
16- or 32-bit ROM interface running in Fast mode.
DRAM Controller
The integrated DRAM controller provides the signals and
associated timing necessary to support an external
DRAM array with minimal software programming and
overhead. Internal programmable registers are provided
to select the DRAM type and operating mode, as well as
refresh options. A wide variety of commodity DRAMs are
supported, and substantial flexibility is built into the DRAM
controller to optimize performance of the CPU and (on the
élanSC400 microcontroller) the internal graphics control-
ler, which uses system DRAM for its buffers.
The DRAM controller supports the following features:
I
3.3-V, 70-ns DRAMs
I
Up to four banks
I
16-bit or 32-bit banks
I
Up to 64 Mbyte of total memory
I
Self-refresh DRAMs
I
Fast page and Extended Data Out (EDO) DRAMs
I
Two-way interleaved operation among identically
populated banks using fast-page mode devices
I
Mixed depth and width of DRAM banks in non-inter-
leaved mode
I
Symmetrical and asymmetrical DRAM support
Integrated Standard PC/AT Peripherals
The élanSC400 and élanSC410 microcontrollers in-
clude all the standard peripheral controllers that make
up a PC/AT system.
Dual DMA Controllers
Dual, cascaded, 8237A-compatible DMA controllers
provide seven user-definable DMA channels. Of the
seven internal channels, four are 8-bit channels and
three are 16-bit channels. Channel 4 is used for the cas-
cade function.
Any two of the seven channels can be mapped simul-
taneously to external DMA request/acknowledge lines.
The DMA controller on the élanSC400 and élanSC410
microcontrollers is software compatible with the PC/AT
cascaded 8237 controller pair. Its features include:
I
Single, block, and demand transfer modes
I
Enable/disable channel controller
I
Address increment or decrement
I
Software priority
I
64-Mbyte system address space for increased
performance
I
Dynamic clock-enable design for reducing clocked
elements during DMA inactivity
I
Programmable clock frequency for performance
Dual Interrupt Controllers
Dual, cascaded, 8259-compatible programmable
interrupt controllers support 15 user-definable interrupt
levels. Eight external interrupt requests can be mapped
to any of the 15 internal IRQ inputs.
The interrupt controller block includes these features:
I
Software-compatibility with PC/AT interrupt controllers
I
15-level priority controller
I
Programmable interrupt modes
I
Individual interrupt request mask capability
I
Accepts requests from peripherals
I
Resolves priority on pending interrupts and
interrupts in service
I
Issues interrupt request to processor
I
Provides interrupt vectors for interrupt service routines
I
Tied into the PMU for power management
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ELANSC400-33AC-REVA3 | 制造商:Advanced Micro Devices 功能描述:MCU 16-Bit/32-Bit Elan CISC ROMLess 3.3V 292-Pin BGA |
| ELANSC400-33AI | 制造商:Advanced Micro Devices 功能描述:MCU 32-bit Elan RISC ROMLess 3.3V 292-Pin BGA |
| ELANSC400-33AIAD | 制造商:Advanced Micro Devices 功能描述: |
| ELANSC400-66AC | 制造商:Advanced Micro Devices 功能描述: |
| ELANSC400-66AI | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip, Low-Power, PC/AT-Compatible Microcontrollers |
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