參數(shù)資料
型號(hào): ELANSC310
英文描述: Elan SC310 - Elan SC310 Single-Chip. 32-Bit. PC/AT Microcontroller
中文描述: 義隆SC310 -伊蘭SC310單芯片。 32位。的PC / AT單片機(jī)
文件頁(yè)數(shù): 69/119頁(yè)
文件大小: 1167K
代理商: ELANSC310
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lanSC310 Microcontroller Data Sheet
53
PREL IMINARY
Parallel Port Anomalies
General
The lanSC310 microcontroller parallel port can be
physically mapped to three different I/O locations or
can be completely disabled. These I/O locations are
3B(x)h, 37(x)h, and 27(x)h. Typically the system BIOS
or a software driver sets up the port at system boot
time. Generally, LPT1 is set up by software to be asso-
ciated with IRQ7, and LPT2 (and LPT3 if desired) is set
up to be associated with IRQ5. In the lanSC310 mi-
crocontroller, the parallel port is always associated with
IRQ7. This cannot be changed regardless of the I/O lo-
cation to which the parallel port is mapped.
Local Bus or Maximum ISA Configuration
The Parallel Port Address Select Register, Port 3D4h,
Index 20h, controls the parallel port mapping. If the Bus
Mode Initialization Register, port 3D4h, Index 19h, has
been configured to its mandatory bit settings prior to
configuring the Parallel Port Address Select Register,
the parallel port cannot be remapped. This can cause
the system boot sequence to require modification such
that the parallel port is set up prior to Port 3D4h, Index
19h being configured. For more details about this
anomaly, see chapters 3 and 4 of the
lanTMSC310
Programmer’s Reference Manual, order #20665.
PC/AT Support Features
The lanSC310 microcontroller provides all of the sup-
port functions found in the original PC/AT. These in-
clude the Port B status and control bits, speaker
control, extensions for fast reset, and A20 gate control.
(Fast CPU reset and fast A20 gate functions are con-
trolled by either the Miscellaneous 1 Register, Index
6Fh, or port 92h). For more information, see Chapter 3
of the
lanTMSC310 Microcontroller Programmer’s
Reference Manual, order #20665.
The lanSC310 microcontroller also includes support
for port B, and a miscellaneous PC/AT register that al-
lows direct programming of the speaker via the SPK
line. In addition, the lanSC310 microcontroller also
generates a chip select and clock source for an exter-
nal, standard 8042 keyboard controller or the PC/XT
keyboard feature.
Note: For more information about the PC/AT and PC/
XT keyboard interface, see Appendix B of the
lanTMSC310 Microcontroller Programmer’s Refer-
ence Manual, order #20665.
Port B and NMI Control
Port B is a PC/AT-standard miscellaneous feature con-
trol register that is located at I/O address 061h. The
lower 4 bits of the 8-bit register are read/write control
bits that enable or disable NMI check condition sources
and sound generation features. The top, or most signif-
icant 4 bits are read/write bits that return status and di-
agnostic information and control the PC/XT keyboard
interface.
There is a master NMI enable function provided that
can inhibit any NMIs from reaching the CPU regardless
of the state of the individual source enables. This mas-
ter NMI control is located as a single bit (7) of the reg-
373 Octal D Transparent Latch
SD7–SD0
Parallel Port
Data Bus
DQ
EN
OE
PPOEN
IOW
IOR
244 type buffer
YA
ENB
PPDCS
Figure 6.
The lanSC310 Microcontroller Bidirectional Parallel Port and EPP Implementation
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