- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄97907 > ELANSC310 Elan SC310 - Elan SC310 Single-Chip. 32-Bit. PC/AT Microcontroller PDF資料下載
參數(shù)資料
| 型號： | ELANSC310 |
| 英文描述： | Elan SC310 - Elan SC310 Single-Chip. 32-Bit. PC/AT Microcontroller |
| 中文描述： | 義隆SC310 -伊蘭SC310單芯片。 32位。的PC / AT單片機 |
| 文件頁數(shù)： | 56/119頁 |
| 文件大?。?/td> | 1167K |
| 代理商： | ELANSC310 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁當前第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁
lanSC310 Microcontroller Data Sheet
41
PREL IMINARY
SRAM
When using SRAM instead of DRAM for main memory,
up to 16 Mbyte can be accessed, the SRAM being or-
ganized as one or two banks. Each bank is 16 bits wide
and is provided with a low and high byte select.
An SRAM memory interface is selected by setting bit 0
of the Miscellaneous 6 Register, Index 70h. If this is
done, CAS1H, CAS1L, CAS0H, and CAS0L will have
their alternate function as SRAM chip select pins 3–0
(SRCS3–SRCS0). Table 17 shows the key SRAM ac-
cess pins.
See Table 14 on page 39 for bank size settings.
The MS2–MS0 bits in the Memory Configuration Reg-
ister, Index 66h, are also used to program the total
SRAM size. Bit 7 of Index Register B4h must be
cleared for SRAM configurations. Table contains infor-
mation about SRAM wait state logic, and Table 28 on
page 61 contains SRAM interface alternate pin infor-
mation.
The PMU Modes and Clock Generators
The Power Management Unit (PMU) monitors all sys-
tem activities (e.g., keyboard, screen, and disk events),
and, based on the state of the system, determines in
which operating mode the system should be running.
The PMU supports six operating modes, each defined
by a different combination of CPU and peripheral oper-
ation, as shown in the list that follows.
1. High-Speed PLL. All clocks are at their fastest
speed and all peripherals are powered up. This is
the mode the system enters when activity is de-
tected by the PMU.
2. Low-Speed PLL. The internal CPU clock is re-
duced to a maximum of 4.608 MHz. All other clocks
and peripherals operate at full speed. This is the
first level of power conservation; it is entered after a
specified elapsed time with no activity.
3. Doze. The second level of power conservation. The
CPU, system, and DMA clocks are stopped. The
high-speed PLL is turned off. This mode is entered
after a specified elapsed time with no activity.
4. Sleep. Additional clocks and peripherals are
stopped after additional inactivity has been de-
tected. The exact parameters can be programmed.
The Low-Speed PLL can be left on, so a quick star-
tup is possible.
5. Suspend. Virtually all of the system is shut down,
including all clocks, the 8254 timer, and the Phase
Locked Loops (a programmable recovery time is
associated with this mode). The 32.768 kHz clock
input is still running.
6. Off. This level is virtually the same as Suspend
mode. Two outputs can be programmed to change
state when the transition from Suspend mode to Off
mode occurs. DRAM refresh can be disabled in
OFF mode.
In addition, the lanSC310 microcontroller can man-
age the power consumption of peripheral devices. This
control can be forced upon entering a specific operat-
ing mode or it can be handled directly by firmware. The
lanSC310 microcontroller PMU controls five power
Table 17.
SRAM Access Pins
Pin Name
I/O
Function
SRCS0
O
SRAM Bank 0 Low Byte Select
SRCS1
O
SRAM Bank 0 High Byte Select
SRCS2
O
SRAM Bank 1 Low Byte Select
SRCS3
O
SRAM Bank 1 High Byte Select
SA23–SA1
O
Address (16-Mbyte maximum)
MWE
0
Write enable
Table 18.
SRAM Wait State Select Logic
Configuration
Number of Wait States
SRAM Speed
Index 63h
Bit 4
Index 66h
Bits 1 and 0
Read
Write
20 MHz
25 MHz
33 MHz
x
0 0
0
1
45ns
35ns
25ns
0
0 1
1
80ns
55ns
35ns
1
0 1
2
120 ns
100 ns
70 ns
Notes:
Refer to Index 70h, bit 0, in the lanTMSC310 Microcontroller Programmer’s Reference Manual, order #20665 for information
on how to select SRAM versus DRAM.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ELANSC410 | Single Synchronous Buck Pulse-Width Modulation (PWM) Controller; Temperature Range: 0°C to 70°C; Package: 16-QFN |
| ELH0032G | Fast Operational Amplifier |
| ELH0033G | Fast Buffer Amplifier |
| ELH0101CK | Dual Regulator-Standard Buck PWM and Linear Power Controller; Temperature Range: 0°C to 70°C; Package: 8-SOIC T&R |
| ELH0101ACK | Single Synchronous Buck Pulse-Width Modulation (PWM) Controller; Temperature Range: -40°C to 85°C; Package: 16-QFN |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ELANSC310-25 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip, 32-Bit, PC/AT Microcontroller |
| ELANSC310-25KC | 制造商:ADVANCED MICRO DEVICES,INC 功能描述: |
| ELANSC310-25KI | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip, 32-Bit, PC/AT Microcontroller |
| ELANSC310-25VC | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Advanced Micro Devices 功能描述: 制造商:AMD 功能描述: |
| ELANSC310-33 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip, 32-Bit, PC/AT Microcontroller |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。