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| 型號(hào)： | ELANSC300-33VC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Highly Integrated, Low-Power, 32-Bit Microcontroller |
| 中文描述： | 32-BIT, 33 MHz, MICROCONTROLLER, PQFP208 |
| 封裝： | TQFP-208 |
| 文件頁(yè)數(shù)： | 36/139頁(yè) |
| 文件大?。?/td> | 1388K |
| 代理商： | ELANSC300-33VC |
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36
élanSC300 Microcontroller Data Sheet
P R E L I M I N A R Y
IOW
I/O Write Command (Output; Active Low)
The IOW signal indicates that the current cycle is a
write of the currently selected I/O device. When this
signal is asserted, the selected I/O device can latch
data from the data bus.
IRQ1, IRQ14 [LCDDL2]
Interrupt Request Channels 1 and 14 (Input; Rising
Edge/Active High, with Internal Pullup)
This input is connected to the internal 8259A-compati-
ble Interrupt Controller Channels 1 and 14. In PC-com-
patible systems, IRQ1 may be connected to the 8042
keyboard controller.
(IRQ14 is available unless the internal LCD Controller
Bus mode is selected and a dual-scan panel interface
is selected via firmware.)
MCS16 [LCDDL1]
(Input; Active Low)
This input is used to signal to the ISA control logic that
the targeted memory device is a 16-bit device.
(MCS16 is available unless the internal LCD Controller
Bus mode is selected and a dual-scan LCD panel inter-
face is selected via firmware.)
MCS16
is generated by a 16-bit memory expansion
card when the card recognizes it is being addressed.
This signal tells the data bus steering logic that the ad-
dressed memory device is capable of communicating
over both data paths. When accessing an 8-bit memory
device, the
MCS16
line remains deasserted, indicating
to the data bus steering logic that the currently ad-
dressed device is an 8-bit memory device capable of
communicating only over the lower data path.
Note:
MCS16
is internally ORed with
IOCS16
. Do not
tie
MCS16
Low.
For more information about the
MCS16
pin, see the
Using 16-Bit
ROMCS
Designs in élan
TM
SC300 and
élanSC310 Microcontrollers Application Note
, order
#21825.
MEMR
Memory Read Command (Output; Active Low)
The MEMR signal indicates that the current cycle is a
read of the currently selected memory device. When
this signal is asserted, the selected memory device can
drive data onto the data bus.
MEMW
Memory Write Command (Output; Active Low)
The MEMW signal indicates that the current cycle is a
write of the currently selected memory device. When
this signal is asserted, the selected memory device can
latch data from the data bus.
PIRQ0 (PIRQ0/IRQ3),
PIRQ1 (PIRQ1/IRQ6)
Programmable Interrupt Requests (Inputs; Rising
Edge/Active High, with Internal Pullup)
These two inputs can be programmed to drive any of
the available interrupt controller interrupt request in-
puts. For more information, see the PIRQ Configura-
tion Register, Index B2h, in the
élan
TM
SC300
Microcontroller Programmer’s Reference Manual
,
order #18470.
RSTDRV
System Reset (Output; Active High)
This signal is the ISA-compatible reset signal. When
this signal is asserted, all connected devices reinitialize
to their reset state. The pulse width of RSTDRV is ad-
justable, based on PLL startup timing. For more infor-
mation, see
“Loop Filters” on page 97 and the power-
up sequence timings beginning on page 99.
SA11–SA0
System Address Bus (Output; Active High)
The system address bus outputs the physical memory
or I/O port, least-significant, latched addresses. They
are used by all external I/O devices and all memory de-
vices other than main system DRAM. During main sys-
tem SRAM and local bus cycles, this bus represents
the CPU address bus (A11–A1). SA0 is equivalent to
A0 during local bus cycles. See MA11–MA0 on
page 34 for SA23–SA12.
SBHE [LCDDL3]
(Output; Active Low)
Active when the high byte is to be transferred on the
upper 8 bits of the data bus.
(SBHE is available unless the internal LCD Controller
Bus mode is selected and a dual-scan LCD panel inter-
face is selected via firmware.)
SPKR
Speaker, Digital Audio Output (Output)
This signal controls an external speaker driver. It is
generated from the internal 8254-compatible Timer
Channel 2 output ANDed with I/O port 061h, bit 1
(speaker data enable).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ELANSC300 | Highly Integrated, Low-Power, 32-Bit Microcontroller |
| ELANSC300-25KC | Highly Integrated, Low-Power, 32-Bit Microcontroller |
| ELANSC300-25KI | Highly Integrated, Low-Power, 32-Bit Microcontroller |
| ELANSC300-25VC | Highly Integrated, Low-Power, 32-Bit Microcontroller |
| ELANSC300-25VI | Highly Integrated, Low-Power, 32-Bit Microcontroller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ELANSC300-33VI | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Highly Integrated, Low-Power, 32-Bit Microcontroller |
| ELANSC300WW WAF | 制造商:Advanced Micro Devices 功能描述: |
| ELANSC310 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Elan SC310 - Elan SC310 Single-Chip. 32-Bit. PC/AT Microcontroller |
| ELANSC310-25 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip, 32-Bit, PC/AT Microcontroller |
| ELANSC310-25KC | 制造商:ADVANCED MICRO DEVICES,INC 功能描述: |
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