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| 型號(hào)： | ELANSC300-33KI |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Highly Integrated, Low-Power, 32-Bit Microcontroller |
| 中文描述： | 32-BIT, 33 MHz, MICROCONTROLLER, PQFP208 |
| 封裝： | SHRINK, PLASTIC, QFP-208 |
| 文件頁(yè)數(shù)： | 35/139頁(yè) |
| 文件大?。?/td> | 1388K |
| 代理商： | ELANSC300-33KI |
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élanSC300 Microcontroller Data Sheet
35
P R E L I M I N A R Y
For more information about the
ROMCS
pin, see the
Using 16-Bit
ROMCS
Designs in élan
TM
SC300 and
élanSC310 Microcontrollers Application Note
, order
#21825.
SYSTEM INTERFACE
AEN [TDI]
DMA Address Enable (Output; Active High)
AEN is used to indicate that the current address active
on the SA23–SA0 address bus is a memory address
and that the current cycle is a DMA cycle. All I/O de-
vices should use this signal in decoding their I/O ad-
dresses and should not respond when this signal is
asserted. When AEN is asserted, the DACKx signals
are used to select the appropriate I/O device for the
DMA transfer.
This is a dual-function pin. When the JTAGEN signal is
asserted, it functions as the TDI, JTAG Test Data Input
pin.
D15–D0
System Data Bus (Bidirectional; Active High)
The System Data Bus inputs data during memory and
I/O read cycles, and outputs data during memory and
I/O write cycles. During Local Bus and DRAM/SRAM
cycles, this bus represents the CPU data bus.
DACK2 [TCK]
DMA Channel 2 Acknowledge (Output; Active Low)
This output indicates that the current transfer is a DMA
transfer to the I/O device connected to this DMA chan-
nel. In PC-compatible system designs, this signal can
be connected to the floppy disk controller DMA ac-
knowledge input.
This is a dual-function pin. When the JTAGEN signal is
asserted, it functions as the TCK (JTAG Test Clock)
pin. See
“JTAG Boundary Scan Interface” on page 44
for more information on the function of this pin during
Test mode.
DBUFOE
Data Buffer Output Enable (Output; Active Low)
This output is used to control the output enable on the
system data bus buffer. When Low, the outputs of the
Data Bus Buffer are enabled.
DRQ2 [TDO]
DMA Channel 2 Request (Input; Active High
with Internal Pulldown)
This input is used to request a DMA transfer. It can be
connected to the floppy disk controller DMA request
output in PC-compatible system designs.
This is a dual-function pin. When the JTAGEN signal is
asserted, it will function as the TDO, JTAG Test Data
Out pin. See “JTAG Boundary Scan Interface” on page
ing Test mode.
ENDIRH
High Byte Data Buffer Direction Control
(Output; Active High)
This output controls the transceiver on the high byte of
the data bus, bits 15–8. When asserted, this signal is
used to enable the data from the élanSC300 microcon-
troller data bus to the buffered data bus.
ENDIRL
Low Byte Data Buffer Direction Control
(Output; Active High)
This output controls the transceiver on the low byte of
the data bus, bits 7–0. When asserted, this signal is
used to enable the data from the élanSC300 microcon-
troller data bus to the buffered data bus.
IOCHRDY
I/O Channel Ready (Input; Active High)
This signal is used by ISA slave devices to add wait
states to the current transfer. When this signal is deas-
serted, wait states are added.
IOCS16 [LCDDL0]
(Input; Active Low)
This input is used to signal to the ISA control logic that
the targeted I/O device is a 16-bit device.
(IOCS16 is available unless the internal LCD Controller
Bus mode is selected and a dual-scan LCD panel inter-
face is selected via firmware.)
IOCS16
is generated by a 16-bit ISA I/O expansion
board when the board recognizes it is being ad-
dressed.
IOCS16
provides the same function for 16-bit
I/O expansion devices as the
MCS16
signal provides for
the 16-bit memory devices.
Note:
IOCS16
is internally OR’d with
MCS16
. Do not tie
IOCS16
Low.
For more information about the
IOCS16
pin, see the
Using 16-Bit
ROMCS
Designs in élan
TM
SC300 and
élanSC310 Microcontrollers Application Note
, order
#21825.
IOR
I/O Read Command (Output; Active Low)
The IOR signal indicates that the current cycle is a read
of the currently selected I/O device. When this signal is
asserted, the selected I/O device can drive data onto
the data bus.
相關(guān)PDF資料 |
PDF描述 |
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| ELANSC300-33VC | Highly Integrated, Low-Power, 32-Bit Microcontroller |
| ELANSC300 | Highly Integrated, Low-Power, 32-Bit Microcontroller |
| ELANSC300-25KC | Highly Integrated, Low-Power, 32-Bit Microcontroller |
| ELANSC300-25KI | Highly Integrated, Low-Power, 32-Bit Microcontroller |
| ELANSC300-25VC | Highly Integrated, Low-Power, 32-Bit Microcontroller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ELANSC300-33VC | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Advanced Micro Devices 功能描述: 制造商:AMD 功能描述: |
| ELANSC300-33VI | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Highly Integrated, Low-Power, 32-Bit Microcontroller |
| ELANSC300WW WAF | 制造商:Advanced Micro Devices 功能描述: |
| ELANSC310 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Elan SC310 - Elan SC310 Single-Chip. 32-Bit. PC/AT Microcontroller |
| ELANSC310-25 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip, 32-Bit, PC/AT Microcontroller |
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