參數(shù)資料
型號(hào): ELANSC300-33KI
廠商: ADVANCED MICRO DEVICES INC
元件分類: 微控制器/微處理器
英文描述: Highly Integrated, Low-Power, 32-Bit Microcontroller
中文描述: 32-BIT, 33 MHz, MICROCONTROLLER, PQFP208
封裝: SHRINK, PLASTIC, QFP-208
文件頁(yè)數(shù): 116/139頁(yè)
文件大?。?/td> 1388K
代理商: ELANSC300-33KI
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116
élanSC300 Microcontroller Data Sheet
P R E L I M I N A R Y
Notes:
1. PCMCIA specifies 20 ns (min) for 5 V I/O cards.
2. If the PCMCIA address buffer is controlled via the MCE signals, the output disable/enable delay of the buffer will affect the
address setup and hold from MEMR.
3. WAIT_AB asserted for greater that 10
μ
s may cause a DRAM RAS
low (max) to be violated if the “extended” PCMCIA cycle
occurs during a DRAM page hit. (See the t
RASC
max parameter for a particular DRAM.) The RAS active timer (10
μ
s) will not
force RAS inactive while the “extended” PCMCIA cycle is occurring.
These timings are based on default device settings and required initial programming. These timings may be modified via the Wait
State Control and Command Delay Register. (See the élan
TM
SC300 Microcontroller Programmer’s Reference Manual
, order
#18470.)
Table 62.
PCMCIA I/O Read Cycle (See Figure 45)
Symbol
Parameter Description
Notes
Version B3
Preliminary
Version B4
Preliminary
Units
Min
Max
Min
Max
t1
Data setup before IOR
40
40
ns
t2
Data hold following IOR
0
0
ns
t3a
IOR width time (8 bit)
560
490
ns
t3b
IOR width time (16 bit)
280
225
ns
t4a
Address setup before IOR (8 bit)
150
150
ns
t4b
Address setup before IOR (16 bit)
115
115
ns
t5
Address hold following IOR
1
–1
50
ns
t6a
MCEL setup before IOR (8 bit)
2
160
160
ns
t6b
MCEL setup before IOR (16 bit)
100
100
ns
t7
MCE hold after IOR
1, 2
5
65
ns
t8
REG setup before IOR
5
5
ns
t9
REG hold after IOR
0
65
ns
t10
IOIS16 delay falling from Address
35
35
ns
t11
IOIS16 delay rising from Address
35
35
ns
t12
WAIT_AB delay falling from IOR
35
35
ns
t13
WAIT_AB pulse width time
3
12,000
12,000
ns
t14
ICDIR setup before IOR
–5
–5
ns
t15
ICDIR hold after IOR
0
5
ns
t16
DBUFOE setup before IOR
–3
–3
ns
t17
DBUFOE hold after IOR
–3
45
ns
t18a
ENDIRH, ENDIRL setup before IOR (8 bit)
170
170
ns
t18b
ENDIRH, ENDIRL setup before IOR (16 bit)
110
110
ns
t19
ENDIRH, ENDIRL hold from IOR
–6
45
ns
t20
MCEH delay from IOIS16 active
50
50
ns
t21
IOR inactive from WAIT_AB inactive
100
100
ns
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