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參數(shù)資料
| 型號： | EL4584CSZ-EVAL |
| 廠商： | Intersil |
| 文件頁數(shù)： | 13/15頁 |
| 文件大小： | 0K |
| 描述： | EVALUATION BOARD FOR EL4584 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計時，PLL |
| 嵌入式： | 否 |
| 已用 IC / 零件： | EL4584CSZ |
| 主要屬性： | 適用于高達(dá) 36 MHz 的視頻 |
| 次要屬性： | 5V 電源，< 2ns 抖動（VCXO） |
| 已供物品： | 板 |
7
FN7174.3
May 9, 2008
Block Diagram
Description Of Operation
The horizontal sync signal (CMOS level, falling leading
edge) is input to HSYNC input (pin 10). This signal is delayed
about 200ns, the falling edge of which becomes the
reference to which the clock output will be locked (see
“Timing Diagrams” on page 5 and page 6). The clock is
generated by the signal on pin 5, OSC IN. There are 2
general types of VCO that can be used with the EL4584; LC
and crystal controlled. Additionally, each type can be either
built-up using discrete components, including a varactor as
the frequency controlling element, or complete, self
contained modules can be purchased with everything inside
a metal can. The modules are very forgiving of PCB layout,
but cost more than discrete solutions. The VCO or VCXO is
used to generate the clock. An LC tank resonator has
greater “pull” than a crystal controlled circuit, but will also be
more likely to drift over time, and thus will generate more
jitter. The “pullability” of the circuit refers to the ability to “pull”
the frequency of oscillation away from its center frequency
by modulating the voltage on the control pin of a VCO
module or varactor, and is a function of the slope and range
of the capacitance-voltage curve of the varactor or VCO
module used. The VCO signal is sent to a divide by N
counter, and to the CLK OUT pin. The divisor N is
determined by the state of pins 1, 2 and 16 and is described
in Table 2. The divided signal is sent, along with the delayed
HSYNC input, to the phase/frequency detector, which
compares the two signals for phase and frequency
differences. Any phase difference is converted to a current at
the charge pump output FILTER (pin 7). A VCO with positive
frequency deviation with control voltage must be used.
Varactors have negative capacitance slope with voltage,
resulting in positive frequency deviation with control voltage
VCO
The VCO should be tuned so its frequency of oscillation is
very close to the required clock output frequency when the
voltage on the varactor is 2.5V. VCXO and VCO modules are
already tuned to the desired frequency, so this step is not
necessary if using one of these units. The range of the
charge pump output (pin 7) is 0V to 5V and it can source or
sink a maximum of about 300A, so all frequency control
FIGURE 10. PACKAGE POWER DISSIPATION VS AMBIENT TEMPERATURE
Typical Performance Curves (Continued)
1.43W
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.4
0.2
0
P
O
WER
DIS
S
IPATION
(W)
0.6
0
25
50
75
100
125
150
AMBIENT TEMPERATURE (°C)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.25W
PDIP16
θJA = +70°C/W
SO16 (0.150”)
θJA = +80°C/W
EL4584
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EL4584CSZ-T13 | 功能描述:鎖相環(huán) - PLL EL4584CSZ H-SYNC GEN LOCK RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| EL4584CSZ-T7 | 功能描述:鎖相環(huán) - PLL EL4584CSZ H-SYNC GEN LOCK RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| EL4585 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Horizontal Genlock, 8FSC |
| EL4585C | 制造商:ELANTEC 制造商全稱:ELANTEC 功能描述:Horizontal Genlock, 8 FSC |
| EL4585CN | 功能描述:IC PLL VIDEO GP 36MHZ 16-DIP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
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