參數(shù)資料
型號: EL4584CSZ-EVAL
廠商: Intersil
文件頁數(shù): 10/15頁
文件大小: 0K
描述: EVALUATION BOARD FOR EL4584
標(biāo)準(zhǔn)包裝: 1
主要目的: 計時,PLL
嵌入式:
已用 IC / 零件: EL4584CSZ
主要屬性: 適用于高達(dá) 36 MHz 的視頻
次要屬性: 5V 電源,< 2ns 抖動(VCXO)
已供物品:
4
FN7174.3
May 9, 2008
Pin Descriptions
PIN NUMBER
PIN NAME
FUNCTION
1, 2, 16
PROG B,
PROG C, PROG A
Digital inputs to select ÷ N value for internal counter. See Table 2 for values.
3
OSC/VCO OUT
Output of internal inverter/oscillator. Connect to external crystal or LC tank VCO circuit.
4
VDD (A)
Analog positive supply for oscillator, PLL circuits.
5
OSC/VCO IN
Input from external VCO.
6
VSS (A)
Analog ground for oscillator, PLL circuits.
7
CHARGE PUMP
OUT
Connect to loop filter. If the HSYNC phase is leading or HSYNC frequency > CLK ÷ N, current is pumped
into the filter capacitor to increase VCO frequency. If HSYNC phase is lagging or frequency < CLK ÷ N,
current is pumped out of the filter capacitor to decrease VCO frequency. During coast mode or when
locked, charge pump goes to a high impedance state.
8
DIV SELECT
Divide select input. When high, the internal divider is enabled and EXT DIV becomes a test pin, outputting
CLK ÷ N. When low, the internal divider is disabled and EXT DIV is an input from an external ÷ N.
9
COAST
Tri-state logic input. Low (<1/3*VCC) = normal mode, Hi Z (or 1/3 to 2/3*VCC) = fast lock mode,
High (>2/3*VCC) = coast mode.
10
HSYNC IN
Horizontal sync pulse (CMOS level) input.
11
VDD (D)
Positive supply for digital, I/O circuits.
12
LOCK DETECT
Lock Detect output. Low level when PLL is locked. Pulses high when out of lock.
13
EXT DIVIDER
External Divide input when DIV SEL is low, internal ÷N output when DIV SEL is high.
14
VSS (D)
Ground for digital, I/O circuits.
15
CLK OUT
Buffered output of the VCO.
TABLE 2. VCO DIVISORS
PROG A (PIN 16)
PROG B (PIN 1)
PROG C (PIN 2)
DIV VALUE (N)
000
851
001
864
010
944
011
1135
100
682
101
858
110
780
111
910
EL4584
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