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    參數(shù)資料
    型號(hào): EFM32TG230F32
    廠商: Energy Micro
    文件頁數(shù): 32/136頁
    文件大?。?/td> 0K
    描述: MCU 32BIT 32KB FLASH 64-QFN
    特色產(chǎn)品: EFM32 Tiny Gecko
    標(biāo)準(zhǔn)包裝: 1
    系列: Tiny Gecko
    核心處理器: ARM? Cortex?-M3
    芯體尺寸: 32-位
    速度: 32MHz
    連通性: EBI/EMI,I²C,IrDA,智能卡,SPI,UART/USART
    外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,DMA,POR,PWM,WDT
    輸入/輸出數(shù): 56
    程序存儲(chǔ)器容量: 32KB(32K x 8)
    程序存儲(chǔ)器類型: 閃存
    RAM 容量: 4K x 8
    電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.8 V
    數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b,D/A 2x12b
    振蕩器型: 外部
    工作溫度: -40°C ~ 85°C
    封裝/外殼: 64-VFQFN 裸露焊盤
    包裝: 標(biāo)準(zhǔn)包裝
    其它名稱: 914-1035-6
    ...the world's most energy friendly microcontrollers
    2011-02-04 - d0002_Rev1.00
    127
    www.energymicro.com
    Should Be Zero (SBZ)
    Write as 0, or all 0s for bit fields, by software. Writing as 1 produces
    Unpredictable results.
    Should
    Be
    Zero
    or
    Preserved (SBZP)
    Write as 0, or all 0s for bit fields, by software, or preserved by writing the
    same value back that has been previously read from the same field on the
    same processor.
    Thread-safe
    In a multi-tasking environment, thread-safe functions use safeguard
    mechanisms when accessing shared resources, to ensure correct operation
    without the risk of shared access conflicts.
    Thumb instruction
    One or two halfwords that specify an operation for a processor to perform.
    Thumb instructions must be halfword-aligned.
    Unaligned
    A data item stored at an address that is not divisible by the number of bytes
    that defines the data size is said to be unaligned. For example, a word stored
    at an address that is not divisible by four.
    Undefined
    Indicates an instruction that generates an Undefined instruction exception.
    Unpredictable (UNP)
    You cannot rely on the behavior. Unpredictable behavior must not represent
    security holes. Unpredictable behavior must not halt or hang the processor,
    or any parts of the system.
    Warm reset
    Also known as a core reset. Initializes the majority of the processor excluding
    the debug controller and debug logic. This type of reset is useful if you are
    using the debugging features of a processor.
    WA
    See Write-allocate.
    WB
    See Write-back.
    Word
    A 32-bit data item.
    Write
    Writes are defined as operations that have the semantics of a store. Writes
    include the Thumb instructions STM, STR, STRH, STRB, and PUSH.
    Write-allocate (WA)
    In a write-allocate cache, a cache miss on storing data causes a cache line
    to be allocated into the cache.
    Write-back (WB)
    In a write-back cache, data is only written to main memory when it is forced
    out of the cache on line replacement following a cache miss. Otherwise,
    writes by the processor only update the cache. This is also known as
    copyback.
    Write buffer
    A block of high-speed memory, arranged as a FIFO buffer, between the
    data cache and main memory, whose purpose is to optimize stores to main
    memory.
    Write-through (WT)
    In a write-through cache, data is written to main memory at the same time
    as the cache is updated.
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