參數(shù)資料
型號(hào)： EFM32TG230F32
廠商： Energy Micro
文件頁數(shù)： 135/136頁
文件大?。?/td> 0K
描述： MCU 32BIT 32KB FLASH 64-QFN
特色產(chǎn)品： EFM32 Tiny Gecko
標(biāo)準(zhǔn)包裝： 1
系列： Tiny Gecko
核心處理器： ARM? Cortex?-M3
芯體尺寸： 32-位
速度： 32MHz
連通性： EBI/EMI，I²C，IrDA，智能卡，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，DMA，POR，PWM，WDT
輸入/輸出數(shù)： 56
程序存儲(chǔ)器容量： 32KB（32K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 4K x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 3.8 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b，D/A 2x12b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-VFQFN 裸露焊盤
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： 914-1035-6
...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
98
www.energymicro.com
Bits
Name
Type
Function
[25]
PENDSTCLR
WO
SysTick exception clear-pending bit.
Write:
0 = no effect1 = removes the pending state from the SysTick exception.
This bit is WO. On a register read its value is Unknown.
[24]
-
Reserved.
[23]
Reserved for
Debug use
RO
This bit is reserved for Debug use and reads-as-zero when the processor is not in
Debug.
[22]
ISRPENDING
RO
Interrupt pending flag, excluding NMI and Faults:
0 = interrupt not pending1 = interrupt pending.
[21:18]
-
Reserved.
[17:12]
VECTPENDING
RO
Indicates the exception number of the highest priority pending enabled exception:
0 = no pending exceptions
Nonzero = the exception number of the highest priority pending enabled
exception.
The value indicated by this field includes the effect of the BASEPRI and
FAULTMASK registers, but not any effect of the PRIMASK register.
[11]
RETTOBASE
RO
Indicates whether there are preempted active exceptions:
0 = there are preempted active exceptions to execute
1 = there are no active exceptions, or the currently-executing exception is the only
active exception.
[10:9]
-
Reserved.
[8:0]
VECTACTIVE
1
RO
Contains the active exception number:
0 = Thread mode
Nonzero = The exception number
1 of the currently active exception.
Note
Subtract 16 from this value to obtain the IRQ number required to index
into the Interrupt Clear-Enable, Set-Enable, Clear-Pending, Set-Pending,
or Priority Registers, see Table 2.5 (p. 10) .
1This is the same value as IPSR bits[8:0], see Section 2.1.3.5.2 (p. 10) .
When you write to the ICSR, the effect is Unpredictable if you:
write 1 to the PENDSVSET bit and write 1 to the PENDSVCLR bit
write 1 to the PENDSTSET bit and write 1 to the PENDSTCLR bit.
4.3.5 Vector Table Offset Register
The VTOR indicates the offset of the vector table base address from memory address 0x00000000.
See the register summary in Table 4.12 (p. 94) for its attributes.
The bit assignments are:
31 30 29
7 6
0
TBLOFF
Reserved
Reserved in som e devices
(See not e below)
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