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參數(shù)資料
| 型號(hào)： | EDI8L21665V |
| 英文描述： | 2x64Kx16 SRAM(2x64Kx16靜態(tài)RAM) |
| 中文描述： | 2x64Kx16的SRAM（靜態(tài)RAM的2x64Kx16） |
| 文件頁(yè)數(shù)： | 1/5頁(yè) |
| 文件大?。?/td> | 138K |
| 代理商： | EDI8L21665V |
1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
EDI8L21665V
February 1999 Rev. 0
ECO #
DESCRIPTION
The EDI8L21665VxxBC is a 3.3V, 2x64Kx16 SRAM constructed
with two 64Kx16 die mounted on a multi-layer laminate substrate.
The device is packaged in a 74 lead, 15mm by 15mm, BGA.
Operating with a 3.3V power supply and with access times as fast
as 10ns, the device allows the user to develop a fast external
memory for Texas Instuments’ TMS320C5x DSP.
The device consists of two separate banks of 64Kx16 of memory.
Each bank has a separate Chip Enable pin and higher order
address select pin. Bank ‘A’ is controlled using CE1\ and A15A.
Bank ‘B’ is controlled using CE2\ and A15B. The two banks have
common I/Os (DQ0-15) and control lines (WE\, E\ and G\). E\
connects to the mstrb\ pin of the C54x DSPs and is required for
write and read timing control.
FEATURES
s Access Times of 10, 12 and 15ns
s DSP Memory Solution
Texas Instruments TMS320C5x
s Packaging:
74 pin BGA, JEDEC MO-151
s 3.3V Operating Supply Voltage
s Single Write Control and Output Enable Lines
s One Chip Enable Line per Memory Bank
s 50% Space Savings vs. Monolithic TSOPs
s Upgrade Path Available in Same Footprint
s Multiple VCC and VSS Pins
s Reduced Inductance and Capacitance
BLOCK DIAGRAM
PIN CONFIGURATION
A0-14
G
W
CE1
A15A
E
G
CE
A15
CE
A15
CE2
A15A
64K X 16
SSRAM
64K X 16
SSRAM
U1
U2
123
4
56789
10
11
A
Vss
Vcc
Vcc DQ15 DQ14 Vcc DQ13 DQ11 DQ9
DQ8
NC
A
B
Vss
Vcc
Vcc Vss
Vss
Vcc DQ12 DQ10 DQ4
Vcc
B
C
Vss
Vcc
Vss
Vcc
C
D
Vss
Vcc
D
E
Vss
Vcc
E
F A15A
CE1
DQ3 DQ7
F
G
EW
DQ5 DQ0 G
H
Vss
CE2
DQ6 DQ1 H
I
Vss
A14
Vcc
DQ2
NC
I
J
Vss
A12
Vcc
A10
A8
Vss
A6
A4
A2
A0
G
J
K A15B
A13
Vcc
A11
A9
Vss
A7
VSS
A5
A3
A1
K
123
4
56789
10
11
2x64Kx16 SRAM, DSP Memory Solution
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