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參數(shù)資料
| 型號： | EDI8L3265C |
| 英文描述： | 64Kx32 CMOS High Speed Static RAM(64Kx32高速CMOS靜態(tài)RAM) |
| 中文描述： | 64Kx32的CMOS高速靜態(tài)隨機存儲器（64Kx32高速的CMOS靜態(tài)RAM）的 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大小： | 101K |
| 代理商： | EDI8L3265C |
EDI8L3265C
64Kx32 SRAM
1
EDI8L3265C Rev. 4 3/97 ECO #8302
64Kx32 CMOS High Speed
Static RAM
The EDI8L3265C is a high speed, high performance, four
megabit density Static RAM organized as a 64Kx32 bit
array.
Four Byte Selects, two Chip Enables, Write Control, and
Output Enable provide the user with a flexible memory
solution. The user may independently enable each of the
four bytes, and, with minimal additional peripheral logic, the
unit may be configured as a 128Kx16 array.
Fully asynchronous circuitry is used, requiring no clocks or
refreshing for operation and providing equal access and
cycle times for ease of use.
The EDI8L3265C, allows 2 megabits of memory to be
placed in less than 0.990 square inches of board space. The
EDI8L3265C can be upgraded to 128K, 256K or 512Kx32
in the same footprint using the EDI8L32128, EDI8L32256 or
the EDI8L32512C. (See page 6 for upgrade paths).
Features
64Kx32 bit CMOS Static
Random Access Memory Array
Fast Access Times: 12*, 15, 20, and 25ns
Individual Byte Selects
User Configurable Organization
with Minimal Additional Logic
Master Output Enable and Write Control
TTL Compatible Inputs and Outputs
Fully Static, No Clocks
Surface Mount Package
68 Lead PLCC, No. 99 (JEDEC-M0-47AE)
Small Footprint, 0.990 Sq. In.
Multiple Ground Pins for Maximum
Noise Immunity
Single +5V (±5%) Supply Operation
Pin Names
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
DQ17
DQ18
DQ19
VSS
DQ20
DQ21
DQ22
DQ23
VCC
DQ24
DQ25
DQ26
DQ27
VSS
DQ28
DQ29
DQ30
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
DQ14
DQ13
DQ12
VSS
DQ11
DQ10
DQ9
DQ8
VCC
DQ7
DQ6
DQ5
DQ4
VSS
DQ3
DQ2
DQ1
DQ31
27
A6
28
A5
29
A4
30
A3
31
A2
32
A1
33
A
34
VCC
35
A13
36
A12
37
A11
38
A10
39
A9
40
A8
41
A7
42
DQ
43
9
DQ16
8N
C
7N
C
6
BS3\
5
BS2\
4
BS1\
3
BS\
2E
1\
1V
C
68
N
C
67
E\
66
G
\
65
W
\
64
N
C
63
A15
62
A14
61
DQ15
A-A15
Address Inputs
E-E1
Chip Enables (one per word)
BS-BS3
Byte Selects (One per Byte)
W
Master Write Enable
G
Master Output Enable
DQ-DQ31
Common Data Input/Output
VCC
Power (+5V±5%)
VSS
Ground
NC
No Connection
A-A15
G
W
E
E1
BS
BS1
BS2
BS3
DQ-DQ7
DQ8-DQ15
DQ16-DQ23
DQ24-DQ31
16
64Kx32
Memory
Array
Pin Configurations and Block Diagram
Notes: 1. See page 6 for upgrade paths.
Electronic Designs Incorporated
One Research Drive Westborough, MA 01581 USA 508-366-5151 FAX 508-836-4850
http://www.electronic-designs.com
* Advance Information
Note: Solder Reflow temperatures should not exceed 260°C for 10 seconds.
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