參數(shù)資料
型號(hào): EDI416S4030A12SI
英文描述: 1Mx 16 Bits x 4 Banks Synchronous DRAM(83MHz,1M x 16 位 x 4 組同步動(dòng)態(tài)RAM)
中文描述: 1Mx 16位× 4個(gè)銀行同步DRAM(83MHz,100萬(wàn)× 16位× 4個(gè)組同步動(dòng)態(tài)RAM)的
文件頁(yè)數(shù): 5/26頁(yè)
文件大?。?/td> 353K
代理商: EDI416S4030A12SI
13
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
EDI416S4030A
June 2000 Rev. 0
FIG. 4 READ & WRITE CYCLE AT SAME BANK @ BURST LENGTH=4
RAS
CAS
ADDR
BA
DQM
A10/AP
CKE
CLOCK
CE
Rb
Cb0
Ca0
Ra
CL = 2
DQ
Row Active
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
Precharge
(A-Bank)
Read
(A-Bank)
Row Active
(A-Bank)
WE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
HIGH
tRCD
tRC
Rb
Note 1
Ra
Qa0
tSHZ
tRDL
tRAC
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
CL = 3
Qa0
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
tSAC
tOH
Note 3
Note 4
Note 3
DON'T CARE
Note 2
NOTES:
1. Minimum row cycle times are required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. (CAS Latency - 1) number of valid output
data is available after Row precharge. Last valid output will be Hi-Z(tSHZ) after the clock.
3. Access time from Row active command. tCC *(tRCD + CAS latency - 1) + tSAC.
4. Output will be Hi-Z after the end of burst (1, 2, 4, 8 & full page bit burst).
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