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參數(shù)資料
| 型號： | EDI416S4030A12SI |
| 英文描述： | 1Mx 16 Bits x 4 Banks Synchronous DRAM(83MHz,1M x 16 位 x 4 組同步動態(tài)RAM) |
| 中文描述： | 1Mx 16位× 4個銀行同步DRAM（83MHz，100萬× 16位× 4個組同步動態(tài)RAM）的 |
| 文件頁數(shù)： | 24/26頁 |
| 文件大?。?/td> | 353K |
| 代理商： | EDI416S4030A12SI |
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7
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
EDI416S4030A
June 2000 Rev. 0
NOTES:
1. For the given Current State CKE must be low in the previous cycle.
2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for CKE (tCKS) must be
satisfied before any command other than Exit is issued.
3. The address inputs (A12-0) depend on the command that is issued. See the Idle State section of the Current State Truth Table for more information.
4. The Power Down Mode, Self Refresh Mode, and the Mode Register Set can only be entered from the all banks idle state.
Must be a legal command as defined in the Current State Truth Table.
CLOCK ENABLE (CKE0) TRUTH TABLE
H
X
INVALID
1
L
H
X
Exit Self Refresh with Device Deselect
2
L
H
L
H
X
Exit Self Refresh with No Operation
2
Self Refresh
L
H
L
H
L
X
ILLEGAL
2
L
H
L
H
L
X
ILLEGAL
2
L
H
L
X
ILLEGAL
2
L
X
Maintain Self Refresh
H
X
INVALID
1
Power Down
L
H
X
Power Down Mode exit, all banks idle
2
L
H
L
X
ILLEGAL
2
L
X
Maintain Power Down Mode
HH
H
X
HH
L
H
X
Refer to the Idle State section of the
3
HH
L
H
X
Current State Truth Table
H
L
H
X
CBR Refresh
H
L
OP Code
Mode Register Set
4
All Banks Idle
H
L
H
X
HL
L
H
X
Refer to the Idle State section of the
3
HL
L
H
X
Current State Truth Table
H
L
H
X
Entry Self Refresh
4
H
L
OP Code
Mode Register Set
L
X
Power Down
4
H
XX
Refer to the Operations in the Current
State Truth Table
Any State other
H
L
X
Begin Clock Suspend next cycle
5
than listed above
L
H
X
Exit Clock Suspend next cycle
L
X
Maintain Clock Suspend
Current State
CKE
Command
Action
Notes
Previous
Current
CE
RAS
CAS
WE
BA
A0-11
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