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參數(shù)資料
| 型號： | EDI416S4030A12SI |
| 英文描述： | 1Mx 16 Bits x 4 Banks Synchronous DRAM(83MHz,1M x 16 位 x 4 組同步動態(tài)RAM) |
| 中文描述： | 1Mx 16位× 4個銀行同步DRAM（83MHz，100萬× 16位× 4個組同步動態(tài)RAM）的 |
| 文件頁數(shù)： | 23/26頁 |
| 文件大小： | 353K |
| 代理商： | EDI416S4030A12SI |
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6
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
EDI416S4030A
June 2000 Rev. 0
Register
Mode Register Set
H
X
L
X
OP CODE
Refresh
Auto(CBR)
H
Entry Self
L
Precharge
Single Bank
H
XL
L
H
L
X
BA
L
X
2
All Banks
XH
X
Bank Activate
H
X
L
H
X
BA
Row Address
2
Write
Auto Precharge Disable
HX
L
H
L
X
BA
L2
Auto Precharge Enable
H2
Read
Auto Precharge Disable
L2
Auto Precharge Enable
H2
Burst Stop
H
X
L
H
L
X
3
No Operation
H
X
L
H
X
Device Deselect
H
X
H
X
Clock Suspend/Standby Mode
L
X
XXXX
XXX
X
4
Data
Write/Output Enable
H
X
XXXX
L
XX
X
5
Mask/Output Disable
H
5
Power Down Mode
Entry
X
L
H
XXX
X
6
Exit
H
6
NOTES:
1. All of the SDRAM operations are defined by states of CE, WE, RAS, CAS, and DQM at the positive rising edge of the clock.
2. Bank Select (BA), if BA0, BA1 = 0, 0 then bank A is selected, if BA0, BA1 = 1, 0 then bank B, if BA0, BA1 = 0, 1 then bank C, if BA0, BA1 = 1, 1 then bank D is
selected, respectively.
3. During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS latency.
4. During normal access mode, CKE is held high and CLK is enabled. When it is low, it freezes the internal clock and extends data Read and Write operations.
One clock delay is required for mode entry and exit.
5. The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high at a clock timing the data outputs are
disabled and become high impedance after a two clock delay. DQM also provides a data mask function for Write cycles. When it activates, the Write operation
at the clock is prohibited (zero clock latency).
6. All banks must be precharged before entering the Power Down Mode. The Power Down Mode does not perform any Refresh operations, therefore the device
can't remain in this mode longer than the Refresh period (tREF) of the device. One clock delay is required for mode entry and exit.
Command
CKE
CE
RAS
CAS
WE
DQM
BA
Previous Current
A10/Ap
A11, A9-0
Notes
Cycle
COMMAND TRUTH TABLE
H
LLL
H
X
H
X
L
H
L
H
X
BA
Column
Address
Column
Address
(X = Don't Care, H = Logic High, L = Logic Low)
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