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參數(shù)資料
| 型號： | EDGE4707B |
| 英文描述： | Edge4707B PPMU Settling Time & Stability (224k) |
| 中文描述： | Edge4707B PPMU建立時間 |
| 文件頁數(shù)： | 9/13頁 |
| 文件大?。?/td> | 224K |
| 代理商： | EDGE4707B |
5
TEST AND MEASUREMENT PRODUCTS
www .semtech.com
PMU-A2
Edge4707B PPMU
Settling Time and Stability
Revision 1 / November 8, 2002
Figure 5. Range D (2mA) Force Output Settling in Force Voltage Mode (CLOAD = 108 pF)
10V step Force output settling characteristic
Range D
-2
0
2
4
6
8
10
0.E+00
5.E-06
1.E-05
2.E-05
3.E-05
4.E-05
Time (sec)
C1-2=0pF, C4=0pF
c1-2=0pF, C4=47pF
c1-2=47pF, c4=0pF
c1-2=47pF, c4=47pF
c1-2=100pF, c4=100pF
Slew Rate Component
As can be seen from Figures 2 though 5, the values of the
compensation capacitors (COMP1-2 and COMP4) have
virtually no effect on the output slew rate except on the
lowest current range. However, as will be seen later, these
capacitors have a marked effect on the final settling time
as well as stability on all ranges.
Therefore, it is
recommended that these capacitors not be modified to
optimize the Range A slew rate in most applications.
In most situations, the driver amplifier slew rate has the
greatest impact on the total settling time when the output
voltage step is large and one of the lower current ranges
is selected. Figure 6 shows settling with varying the FORCE
output voltage step size. On ranges C and D the step size
has little effect on settling time. However, the step size
has significant impact on the settling time on the two
lower current ranges. To optimize system performance, it
is therefore recommended that the voltage step size be
minimized
on the two lower current ranges whenever
possible
(Note: all information presented here was
obtained using the sense resistors recommended in the
Edge4707B data sheet. Any change in these resistor
values may significantly change the performance described
here).
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