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參數(shù)資料
| 型號： | EDI22AG27264V85D1 |
| 英文描述： | 2x64Kx72, 3.3V Synchronous/Synchronous Burst SRAM Module(2x64Kx72, 3.3V，8.5ns,同步/同步脈沖靜態(tài)RAM模塊) |
| 中文描述： | 2x64Kx72，3.3同步/同步突發(fā)靜態(tài)存儲器模塊（2x64Kx72，3.3伏，8.5ns，同步/同步脈沖靜態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 1/11頁 |
| 文件大小： | 231K |
| 代理商： | EDI22AG27264V85D1 |
EDI2AG27264V
1 Megabyte Sync/Sync Burst,
Small Outline DIMM
1
EDI2AG27264V Rev. 0 1/98 ECO#
The EDI2AG27264VxxD1 is a Synchronous/Synchro-
nous Burst SRAM, 72 position SO-DIMM (144 contacts)
Module, organized as 2x64Kx72. The Module contains
four(4) Synchronous Burst Ram Devices, packaged in the
industry standard JEDEC 14mmx20mm TQFP placed on
a Multilayer FR4 Substrate. The module architecture is
defined as a Sync/Sycn Burst, Flow-Through, with support
for linear burst. This module provides High Performance, 2-
1-1-1 accesses when used in Burst Mode, and used as a
Synchronous Only Mode, provides a high performance cost
advantage over BiCMOS aysnchronous device architec-
tures.
Synchronous Only operations are performed via strap-
ping ADSC\ Low, and ADSP\ / ADV\ High, which pro-
vides for Ultra Fast Accesses in Read Mode while provid-
ing for internally self-timed Early Writes.
Synchronous/Synchronous Burst operations are in rela-
tion to an externally supplied clock, Registered Address,
Registered Global Write, Registered Enables as well as
an Asynchronous Output enable. This Module has been
defined with full flexibility, which allows individual control
of each of the eight bytes, as well as Quad Words in both
Read and Write Operations.
2x64Kx72 Synchronous, Synchronous Burst
Flow-Through Architecture
Linear Burst MODE
Clock Controlled Registered Bank
Enables (E1\,E2\)
Clock Controlled Byte Write Mode Enable (BWE\)
Clock Controlled Byte Write Enables (BW1\ - BW8\)
Clock Controlled Registered Address
Clock Controlled Registered Global Write (GW\)
Aysnchronous Output Enable (G\)
Internally self-timed Write
Gold Lead Finish
3.3V +10% Operation
Access Speed(s): TKHQV=8.5, 9, 10, 12ns
Common Data I/O
High Capacitance (30pf) drive, at rated Access
Speed
Single total array Clock
Multiple Vcc and Gnd
Advanced
Module Features
DQ0-DQ63
Input/Output Bus
DQP0-DQP7
Parity Bits
A0-A15
Address Bus
E1\, E2\,
Synchronous Bank Enables
BWE\
Byte Write Mode Enable
BW1\-BW8\
Byte Write Enables
Clk
Array Clock
GW\
Synchronous Global write Enable
G\
Asynchronous Output Enable
Vcc
3.3V Power Supply
Vss
Gnd
Pin Names
Electronic Designs Incorporated
One Research Drive Westborough, MA 01581USA 508-366-5151 FAX 508-836-4850
Electronic Designs Europe Ltd. Shelley House, The Avenue Lightwater, Surrey GU18 5RF
United Kingdom 01276 472637 FAX: 01276 473748
http://www.electronic-designs.com
ADVANCED
2x64Kx72, 3.3V
Sync/Sync Burst Flow-Through
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EDI22AG27264V9D2 | 2x64Kx72, 3.3V Synchronous/Synchronous Burst SRAM Module(2x64Kx72, 3.3V，9ns,同步/同步脈沖靜態(tài)RAM模塊) |
| EDI2AG272128V-D1 | SSRAM Modules |
| EDI2AG272129V-D1 | SSRAM Modules |
| EDI2AG272128V10D1 | 2x128Kx72, 3.3V Sync/Sync Burst SRAM Module(2x128Kx72, 3.3V，10ns,同步/同步脈沖靜態(tài)RAM模塊) |
| EDI2AG272128V12D1 | 2x128Kx72, 3.3V Sync/Sync Burst SRAM Module(2x128Kx72, 3.3V，12ns,同步/同步脈沖靜態(tài)RAM模塊) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDI-25 | 制造商:Farnell / Duratool 功能描述:ELECTRONIC DIGITAL INDICATOR |
| EDI2AG272128V10D1 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2 Megabyte Sync/Sync Burst, Small Outline DIMM |
| EDI2AG272128V12D1 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2 Megabyte Sync/Sync Burst, Small Outline DIMM |
| EDI2AG272128V85D1 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2 Megabyte Sync/Sync Burst, Small Outline DIMM |
| EDI2AG272128V9D1 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2 Megabyte Sync/Sync Burst, Small Outline DIMM |
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