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參數(shù)資料
| 型號(hào)： | EDI2AG272129V-D1 |
| 英文描述： | SSRAM Modules |
| 中文描述： | 的SSRAM模塊 |
| 文件頁數(shù)： | 1/11頁 |
| 文件大?。?/td> | 264K |
| 代理商： | EDI2AG272129V-D1 |
EDI2AG272128V
1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
The EDI2AG272128VxxD1 is a Synchronous/Synchronous Burst
SRAM, 72 position DIMM (144 contacts) Module, organized as
2x128Kx72. The Module contains four (4) Synchronous Burst
Ram Devices, packaged in the industry standard JEDEC
14mmx20mm TQFP placed on a Multilayer FR4 Substrate. The
module architecture is defined as a Sync/Sync Burst, Flow-
Through, with support for linear burst. This module provides High
Performance, 2-1-1-1 accesses when used in Burst Mode, and
used as a Synchronous Only Mode, provides a high performance
cost advantage over BiCMOS aysnchronous device architec-
tures.
Synchronous Only operations are performed via strapping ADSC\
Low, and ADSP\ / ADV\ High, which provides for Ultra Fast
Accesses in Read Mode while providing for internally self-timed
Early Writes.
Synchronous/Synchronous Burst operations are in relation to an
externally supplied clock, Registered Address, Registered Global
Write, Registered Enables as well as an Asynchronous Output
enable. This Module has been defined with full flexibility, which
allows individual control of each of the eight bytes, as well as
Quad Words in both Read and Write Operations.
* This data sheet describes a product that may or may not be under development
and is subject to change or cancellation without notice.
FEATURES
s 2x128Kx72 Synchronous, Synchronous Burst
s Access Speed(s): TKHQV = 8.5, 9, 10, 12ns
s Flow-Through Architecture
s Linear Burst Mode
s Clock Controlled Registered Bank Enables (E1\, E2\)
s Clock Controlled Byte Write Mode Enable (BWE\)
s Clock Controlled Byte Write Enables (BW1\ - BW8\)
s Clock Controlled Registered Address
s Clock Controlled Registered Global Write (GW\)
s Aysnchronous Output Enable (G\)
s Internally self-timed Write
s Gold Lead Finish
s 3.3V
±10% Operation
s Common Data I/O
s High Capacitance (30pF) drive, at rated Access Speed
s Single total array Clock
s Multiple Vcc and Vss
July 1998 Rev.
ECO#
2x128Kx72, 3.3V Sync/Sync Burst SRAM SO-DIMM
ADVANCED*
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EDI2AG272128V10D1 | 2x128Kx72, 3.3V Sync/Sync Burst SRAM Module(2x128Kx72, 3.3V，10ns,同步/同步脈沖靜態(tài)RAM模塊) |
| EDI2AG272128V12D1 | 2x128Kx72, 3.3V Sync/Sync Burst SRAM Module(2x128Kx72, 3.3V，12ns,同步/同步脈沖靜態(tài)RAM模塊) |
| EDI2AG272128V85D1 | 2x128Kx72, 3.3V Sync/Sync Burst SRAM Module(2x128Kx72, 3.3V，8.5ns,同步/同步脈沖靜態(tài)RAM模塊) |
| EDI2AG272128V9D1 | 2x128Kx72, 3.3V Sync/Sync Burst SRAM Module(2x128Kx72, 3.3V，9ns,同步/同步脈沖靜態(tài)RAM模塊) |
| EDI2AG272129V10D1 | 2x128Kx72, 3.3V,10ns, Sync/Sync Burst SRAM Module(2x128Kx72, 3.3V，10ns,同步/同步脈沖靜態(tài)RAM模塊) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDI2CG272128V | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2x128Kx72, 3.3V Sync/Sync Burst SRAM SO-DIMM |
| EDI2CG272128V12D1 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2x128Kx72, 3.3V Sync/Sync Burst SRAM SO-DIMM |
| EDI2CG272128V15D1 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2x128Kx72, 3.3V Sync/Sync Burst SRAM SO-DIMM |
| EDI2CG272128V85D1 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2x128Kx72, 3.3V Sync/Sync Burst SRAM SO-DIMM |
| EDI2CG272128V9D1 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2x128Kx72, 3.3V Sync/Sync Burst SRAM SO-DIMM |
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