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參數(shù)資料
| 型號： | EDGE4707B |
| 英文描述： | Edge4707B PPMU Settling Time & Stability (224k) |
| 中文描述： | Edge4707B PPMU建立時(shí)間 |
| 文件頁數(shù)： | 11/13頁 |
| 文件大?。?/td> | 224K |
| 代理商： | EDGE4707B |
7
TEST AND MEASUREMENT PRODUCTS
www .semtech.com
PMU-A2
Edge4707B PPMU
Settling Time and Stability
Revision 1 / November 8, 2002
The COMP1-2 capacitor shown in Figure 1 provides
negative feedback to the Driver Amplifier at short time
intervals. This keeps the Driver Amplifier stable until the
R-C time constant caused by the sense resistor and
capacitance on the FORCE output begins to provide
feedback through the SENSE input. Small capacitor values
provide less feedback which allows the Driver to operate
faster, but also yield more overshoot and ringing at the
FORCE and IVMON outputs. If the amplitude of the ringing
is larger than the accuracy of the desired measurement,
this will increase the time needed before the measurement
can be made. Larger capacitors can reduce or eliminate
the overshoot, but also slow down the response time, which
increases the final settling time. So, as the value of this
compensation capacitor is increased (starting at a very
low capacitance), the settling time usually increases while
the amount of overshoot and ringing increases. Table 1
shows typical IVMON output settling times for a 2V step
on FORCE output. As described earlier, the value of this
compensation capacitor has less effect on larger step sizes.
The optimum capacitor will vary depending on other factors
such as load capacitance on the FORCE output, the
amount of overshoot which is acceptable in the application,
and the accuracy of the desired measurement. Note that
since continually decreasing COMP1-COMP2 increases the
overshoot and ringing, reducing this capacitor too much
will eventually cause increased settling time.
If this
capacitor is eliminated entirely, settling time becomes
infinite on ranges B and C because the ringing never
dampens out.
Table 1. 0.1% Measure Current (IVMON) Settling Time
Change with Changing COMP1-2 Capacitance
(COMP4 = 22pF, Load Capacitance = 100pF,
Force Step Voltage = 2V)
2
-
1
P
M
O
C
)
F
p
(
A
e
g
n
a
R
)
s
(
B
e
g
n
a
R
)
s
(
C
e
g
n
a
R
)
s
(
D
e
g
n
a
R
)
s
(
04
6
46
.
1
68
.
9
24
.
3
2
26
9
42
.
5
66
.
0
38
.
4
3
36
3
52
.
5
44
.
1
38
.
5
3
7
46
1
64
.
6
66
.
5
38
.
0
4
8
64
0
76
.
7
80
.
6
48
.
0
5
0
12
9
74
.
0
88
.
8
66
.
1
7
The COMP4 capacitor is in parallel with the external sense
resistor when in Force Voltage mode, as shown in
Figure 1. This capacitor is disconnected from the circuit
by an internal switch when the Edge4707B is in the Force
Current mode. The purpose of this capacitor is to allow
fast-slewing signals to bypass the sense resistor, which
improves the slew rate at the FORCE output. This has the
greatest effect when the sense resistor is large, such as
on Range A or B. Typical variation of IVMON settling time
with changing COMP4 capacitor value is shown in
Table 2.
Table 2. IVMON Settling Time with Changing COMP4
Capacitor Value. (COMP1-2=22, Load Cap=108pF,
Force Step Size=2V)
Note that while increasing the size of this capacitor
improves the settling time on the lowest current ranges, it
can also degrade the settling time on the higher current
ranges.
The reason is that this capacitor acts as an
impedance in parallel with the sense resistor. When the
output voltage of the Driver Amplifier suddenly changes,
the impedance of this capacitor will be relatively low, so
the impedance across which the differential amplifier is
measuring will be less than the sense resistor value. After
a period of time, the current through the capacitor will
decrease and the impedance increase. After enough time
has elapsed, the impedance of the parallel capacitor
becomes high enough so its contribution can be ignored.
Larger capacitors have lower impedances at identical
frequencies, so the larger capacitors have longer delay
times before their contribution to the measurement
impedance can be ignored. This contribution is significant
on the higher current ranges primarily due to the shorter
settling times of these ranges. The optimum value for
this capacitor will then depend on how often the low versus
4
P
M
O
C
)
F
p
(
A
e
g
n
a
R
)
s
(
B
e
g
n
a
R
)
s
(
C
e
g
n
a
R
)
s
(
D
e
g
n
a
R
)
s
(
2
26
9
42
.
5
66
.
0
38
.
4
3
34
2
52
.
3
68
.
0
36
.
5
3
7
48
0
66
.
9
64
.
0
36
.
4
3
8
62
1
76
.
1
86
.
1
30
.
5
3
0
12
9
76
.
3
92
.
2
36
.
4
3
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