參數(shù)資料
型號(hào): EDE2508ABSE-GE
廠商: Elpida Memory, Inc.
英文描述: 256M bits DDR2 SDRAM for HYPER DIMM
中文描述: 256M比特的超DDR2 SDRAM的內(nèi)存
文件頁(yè)數(shù): 32/66頁(yè)
文件大?。?/td> 708K
代理商: EDE2508ABSE-GE
EDE2508ABSE, EDE2516ABSE
For proper operation of adjust mode, WL = RL
1 = AL + CL
1 clocks and tDS/tDH should be met as the Output
Impedance Control Register Set Cycle. For input data pattern for adjustment, DT0 to DT3 is a fixed order and not
affected by MRS addressing mode (i.e. sequential or interleave).
Preliminary Data Sheet E0573E30 (Ver. 3.0)
32
Command
EMRS
OCD adjust mode
OCD calibration mode exit
NOP
DT0
tDS tDH
DT1
DT2
DT3
NOP
EMRS
CK
/CK
WL
tWR
DQS, /DQS
DQ_in
Output Impedance Control Register Set Cycle
Drive Mode
Drive mode, both drive (1) and drive (0), is used for controllers to measure DDR2 SDRAM Driver impedance before
OCD impedance adjustment. In this mode, all outputs are driven out tOIT after “Enter drive mode” command and all
output drivers are turned-off tOIT after “OCD calibration mode exit” command as the ”O(jiān)utput Impedance
Measurement/Verify Cycle”.
Command
Enter drivemode
OCD Calibration mode exit
NOP
CK
/CK
DQS, /DQS
High-Z
High-Z
DQs high for drive (1)
DQs low for drive (0)
tOIT
DQ
EMRS
EMRS
tOIT
DQs high and /DQS low for drive (1), DQs low and /DQS high for drive (0)
Output Impedance Measurement/Verify Cycle
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