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參數(shù)資料
| 型號(hào)： | ECOG1 |
| 英文描述： | eCOG1 Microcontroller |
| 中文描述： | eCOG1微控制器 |
| 文件頁(yè)數(shù)： | 6/11頁(yè) |
| 文件大?。?/td> | 277K |
| 代理商： | ECOG1 |
PRELIMINARY
V3.1
www.cyantechnology.com
4
External Memory Interface
Operates as bus Master and Slave
Big-endian or little-endian
Allows both DMA and non DMA
accesses to internal memory and I/O
registers
8, 16 or 32-bit data bus as Master
24-bit address bus as Master
Multiplexed address/data for 16 and 32-
bit data busses as Master
Supports 8-bit and 16-bit transfers as
Slave
16 and 32-bit data bus and accesses as
Slave
Flag Register for software generated
interrupt
Supports up to 128M Single Data Rate
16-bit wide SDRAMs
Four Row/Column SDRAM address
multiplexing schemes
SDRAM auto and self refresh supported
Configurable timing
Low power SDRAM suspend/standby
mode
SDRAM can be mapped into both code
and data space
Single cycle data space access, code
space burst access in conjunction with
Code Cache
Hardware support for software
initialization and refresh of SDRAM
Analog Functions
12-bit ADC with 8KHz sampling,
differential input
On-chip temperature sensor
On-chip Power Supply Monitor
4 channel analog multiplexer with four
input modes:
i)
Four channel inputs to the ADC for
single ended use, using internal
voltage reference
ii)
Three channel inputs to the ADC,
one input as external reference
iii) Three channel inputs to the ADC,
one port as output of the internal
reference voltage
iv) Two differential inputs
IntAct
Amino Communications proprietary
IntAct
interface
Secure, high speed communications
Typically 180Mbit/s data rate
Provides virtual circuit connections
between IntAct devices
Permits inter-processor communications
Clocks
Two crystal oscillators
Low cost 32KHz watch crystal can
generate 25MHz internal clock
Internal PLL
Second oscillator uses a 5MHz crystal
to generate 25MHz internal clock with
low jitter
C Compiler suite
ANSI C Compiler
Validated to ANSI/ISO/FIPS-160
ANSI Standard Library
Macro Assembler
Software Simulator and debugger
eICE Debugger Interface
Real-time debug port
Can program internal Flash
When BREAK command is locked in the
cache, can provide virtually unlimited
address breakpoints
Commands include Reset, Stop, Run,
Run to Break
Non-intrusive read and write to any core
register, including PC
Read and write of any memory location
Power Saving Features
Sleep mode with wake on interrupts
All peripherals have individual clock
domains and can be stopped when not
in use
External Ports
Peripherals are connected to multiple
device pins
Each port has a unique multiplexing
scheme to select port configuration
Two 4-bit ports
Ten 8-bit ports
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