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參數(shù)資料
| 型號： | ECOG1 |
| 英文描述： | eCOG1 Microcontroller |
| 中文描述： | eCOG1微控制器 |
| 文件頁數(shù)： | 4/11頁 |
| 文件大小： | 277K |
| 代理商： | ECOG1 |
PRELIMINARY
V3.1
www.cyantechnology.com
2
CPU Core
16-bit 25MHz register-based core
Harvard architecture
Supports a full array of 16-bit arithmetic
operations, including both signed and
unsigned MULtiply and DIVide
instructions
32MByte linear program memory
128KByte linear data memory
Vectored interrupts
Flash EPROM
64Kbytes organized as 32Kx16
Organized as eight 4Kx16 banks
Individual Flash banks can be read
and/or write protected
Built in programming algorithm is
available under application software
control
Code Cache
512 line cache
Reduces power consumption while
improving performance
Both deterministic and non-deterministic
modes
Individual cache lines can be locked
Can cache both User and Interrupt
Mode
MMU
Performs logical to physical address
translations
Translates between RAM, Program
Memory, and external memory devices
for both code and data accesses
concurrently
Lookup tables in RAM or Flash can be
mapped between each memory area
Up to 2 concurrent translations to
external devices from code addresses
Up to 3 concurrent translations to
external devices from data addresses
Wait states automatically generated
Concurrent accesses to same device
are prioritized
Translations are prioritized to allow
overlapped translations
DUART
Two independent RS232 compatible
asynchronous double-buffered serial
ports
Full modem support (CTS, RTS, DSR,
DTR, DCD, and RI)
Supporting 5, 6, 7, or 8-bits of data
1, 1.5, or 2 stop bits
Even, odd or no parity
Automatic end-of-frame guard time
insertion of 0- to 64-bit periods
Receive time-out detection 0 to 64-bit
periods
Software Line Break generation
Programmable Baud rate generator
Interrupts generated on full and empty
Receiver error detection for false start
bits, parity errors and frame errors
Configurable data polarity
Over-sampling of received data for
noise immunity
DUSART
Two synchronous/asynchronous double-
buffered serial ports
Programmable baud rate generator
End of frame guard time insertion of 0 to
64-bit periods
Receive time-out detection 0 to 64-bit
periods
Receiver error detection for false Start
bits, Parity errors, Frame errors and
Buffer overflow
Configurable data and clock polarity
Configurable data packing, MSB or LSB
first
Over sampling receive data for noise
immunity
Asynchronous Interface:
Asynchronous frames supporting 5, 6, 7,
or 8-bits of data
1, 1.5, or 2 stop bits
Even, odd or no parity
Full modem support (CTS, RTS, DSR,
DTR, DCD, and RI)
Software Line Break generation
Synchronous Interface:
Local or external transmit and receive
clock
Full or half duplex
Frame sizes from 1 to 16-bits with larger
frames possible
Support for NRZ, RZ
PM, PWM and ASK modulation if used
in conjunction with PWM timer
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