參數(shù)資料
型號: EBE11ED8AGFA-4A-E
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 1GB Unbuffered DDR2 SDRAM DIMM (128M words x 72 bits, 2 Ranks)
中文描述: 128M X 72 DDR DRAM MODULE, 0.6 ns, DMA240
封裝: ROHS COMPLIANT, DIMM-240
文件頁數(shù): 11/22頁
文件大?。?/td> 175K
代理商: EBE11ED8AGFA-4A-E
EBE11ED8ABFA
Data Sheet E0379E40 (Ver. 4.0)
11
DC Characteristics 1 (TC = 0 to +85°C, VDD = 1.8V ± 0.1V, VSS = 0V)
Parameter
Operating current
(ACT-PRE)
(Another rank is in IDD2P)
Operating current
(ACT-PRE)
(Another rank is in IDD3N)
Operating current
(ACT-READ-PRE)
(Another rank is in IDD2P)
Symbol Grade
max.
Unit
Test condition
IDD0
-5C
-4A
1080
927
mA
IDD0
-5C
-4A
1575
1395
mA
one bank; tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
IDD1
-5C
-4A
1215
1062
mA
Operating current
(ACT-READ-PRE)
(Another rank is in IDD3N)
IDD1
-5C
-4A
1710
1530
mA
one bank; IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks idle;
tCK = tCK (IDD);
CKE is L;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
CKE is H, /CS is H;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
CKE is H, /CS is H;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
all banks open;
tCK = tCK (IDD);
CKE is L;
Other control and address bus
inputs are STABLE;
Data bus inputs are FLOATING
all banks open;
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
all banks open, continuous burst reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
-5C
180
Precharge power-down
standby current
IDD2P
-4A
144
mA
-5C
450
Precharge quiet standby
current
IDD2Q
-4A
360
mA
-5C
540
Idle standby current
IDD2N
-4A
450
mA
-5C
720
IDD3P-F
-4A
630
mA
Fast PDN Exit
MRS(12) = 0
-5C
450
Active power-down
standby current
IDD3P-S
-4A
360
mA
Slow PDN Exit
MRS(12) = 1
-5C
1170
Active standby current
IDD3N
-4A
1080
mA
Operating current
(Burst read operating)
(Another rank is in IDD2P)
Operating current
(Burst read operating)
(Another rank is in IDD3N)
Operating current
(Burst write operating)
(Another rank is in IDD2P)
Operating current
(Burst write operating)
(Another rank is in IDD3N)
IDD4R
-5C
-4A
1800
1422
mA
IDD4R
-5C
-4A
2295
1890
mA
IDD4W
-5C
-4A
1800
1422
mA
IDD4W
-5C
-4A
2295
1890
mA
all banks open, continuous burst writes;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Auto-refresh current
-5C
-4A
2340
2142
mA
Auto-refresh current
-5C
-4A
2835
2610
mA
tCK = tCK (IDD);
Refresh command at every tRFC (IDD) interval;
CKE is H, /CS is H between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
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EBE11ED8AGFA-5C-E 1GB Unbuffered DDR2 SDRAM DIMM (128M words x 72 bits, 2 Ranks)
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EBE11ED8AGFA-5C-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:1GB Unbuffered DDR2 SDRAM DIMM (128M words x 72 bits, 2 Ranks)
EBE11ED8AGFA-6E-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:1GB Unbuffered DDR2 SDRAM DIMM (128M words x 72 bits, 2 Ranks)
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