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參數(shù)資料
| 型號： | EBD25RB4ALFB-7A |
| 英文描述： | SDRAM|DDR|32MX72|CMOS|DIMM|184PIN|PLASTIC |
| 中文描述： | 內(nèi)存|復(fù)員| 32MX72 |的CMOS |內(nèi)存| 184PIN |塑料 |
| 文件頁數(shù)： | 5/17頁 |
| 文件大?。?/td> | 158K |
| 代理商： | EBD25RB4ALFB-7A |
EBD25RB4ALFB
Data Sheet . E0236E10 (Ver. 1.0)
13
Pin Capacitance (TA = 25°C, VDD, VDDQ = 2.5V ± 0.2V)
Parameter
Symbol
Pins
max.
Unit
Notes
Input capacitance
CI1
Address, /RAS, /CAS, /WE,
/CS, CKE
TBD
pF
Input capacitance
CI2
CLK, /CLK
TBD
pF
Data and DQS input/output
capacitance
CO
DQ, DQS, CB
TBD
pF
AC Characteristics (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V)
Synchronous Characteristics
-7A
-75
-1A
Parameter
Symbol
min.
max.
min.
max.
min.
max.
Unit
Note
Clock cycle time
CL = 2.5
tCK
7.5
12
7.5
12
10
12
ns
CL = 2
7.5
12
10
12
10
12
ns
CLK high-level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
CLK low-level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
DQ output access time from CLK, /CLK
tAC
–0.75
0.75
–0.75
0.75
–0.8
0.8
ns
DQS output access time from CLK, /CLK
tDQSCK –0.75
0.75
–0.75
0.75
–0.8
0.8
ns
DQS-DQ skew (for DQS and associated DQ
signals)
tDQSQ
—
0.5
—
0.5
—
0.6
ns
DQS-DQ skew (for DQS and all DQ signals) tDQSQA —
0.5
—
0.5
—
0.6
ns
Data out low-impedance time from CLK,
/CLK
tLZ
–0.75
0.75
–0.75
0.75
–0.8
0.8
ns
Data out high-impedance time from CLK,
/CLK
tHZ
–0.75
0.75
–0.75
0.75
–0.8
0.8
ns
Half clock period
tHP
tCH, tCL
—
tCH, tCL
—
tCH, tCL —
ns
Read preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
tCK
Read postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
DQ/DQS output hold time from DQS
tQH
tHP –
0.75
—
tHP – 0.75 —
tHP – 1
—
ns
DQ and DM input setup time
tDS
0.5
—
0.5
—
0.6
—
ns
DQ and DM input hold time
tDH
0.5
—
0.5
—
0.6
—
ns
DQ and DM input pulse width (for each
input)
tDIPW
1.75
—
1.75
—
2
—
ns
Write preamble setup time
tWPRES 0
—
0
—
0
—
ns
Write preamble
tWPRE
0.25
—
0.25
—
0.25
—
tCK
Write postamble
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
Write command to first DQS latching
transition
tDQSS
0.75
1.25
0.75
1.25
0.75
1.25
tCK
DQS input high pulse width
tDQSH
0.35
—
0.35
—
0.35
—
tCK
DQS input low pulse width
tDQSL
0.35
—
0.35
—
0.35
—
tCK
DQS falling edge to CLK setup time
tDSS
0.2
—
0.2
—
0.2
—
tCK
DQS falling edge hold time from CLK
tDSH
0.2
—
0.2
—
0.2
—
tCK
Address and control input setup time
tIS
0.9
—
0.9
—
1.1
—
ns
Address and control input hold time
tIH
0.9
—
0.9
—
1.1
—
ns
Address and control input pulse width
tIPW
2.2
—
2.2
—
2.5
—
ns
Internal write to read command delay
tWTR
1
—
1
—
1
—
tCK
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