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參數(shù)資料
| 型號(hào)： | EBD25RB4ALFB-7A |
| 英文描述： | SDRAM|DDR|32MX72|CMOS|DIMM|184PIN|PLASTIC |
| 中文描述： | 內(nèi)存|復(fù)員| 32MX72 |的CMOS |內(nèi)存| 184PIN |塑料 |
| 文件頁數(shù)： | 14/17頁 |
| 文件大小： | 158K |
| 代理商： | EBD25RB4ALFB-7A |
EBD25RB4ALFB
Data Sheet . E0236E10 (Ver. 1.0)
6
Byte No.
Function described
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Hex value
Comments
27
Minimum row precharge time (tRP)
(-7A)
0
1
0
1
0
50H
20ns
(-75)
0
1
0
1
0
50H
20ns
(-1A)
0
1
0
1
0
50H
20ns
28
Minimum row active to row active
delay (tRRD)
(-7A)
0
1
0
3CH
15ns
(-75)
0
1
0
3CH
15ns
(-1A)
0
1
0
3CH
15ns
29
Minimum /RAS to /CAS delay (tRCD)
(-7A)
0
1
0
1
0
50H
20ns
(-75)
0
1
0
1
0
50H
20ns
(-1A)
0
1
0
1
0
50H
20ns
30
Minimum active to precharge time
(tRAS)
(-7A)
0
1
0
1
0
1
2DH
45ns
(-75)
0
1
0
1
0
1
2DH
45ns
(-1A)
0
1
0
1
0
32H
50ns
31
Module bank density
0
1
0
40H
256Mbytes
32
Address and command setup time
before clock (tIS)
(-7A)
1
0
1
0
90H
0.9ns
(-75)
1
0
1
0
90H
0.9ns
(-1A)
1
0
1
0
B0H
1.1ns
33
Address and command hold time after
clock (tIH)
(-7A)
1
0
1
0
90H
0.9ns
(-75)
1
0
1
0
90H
0.9ns
(-1A)
1
0
1
0
B0H
1.1ns
34
Data input setup time before clock
(tDS)
(-7A)
0
1
0
1
0
50H
0.5ns
(-75)
0
1
0
1
0
50H
0.5ns
(-1A)
0
1
0
60H
0.6ns
35
Data input hold time after clock (tDH)
(-7A)
0
1
0
1
0
50H
0.5ns
(-75)
0
1
0
1
0
50H
0.5ns
(-1A)
0
1
0
60H
0.6ns
36 to 61
Superset information
0
00H
Future Use
62
SPD Revision
0
00H
63
Checksum for bytes 0 to 62
(-7A)
1
0
1
0
1
0
A2H
(-75)
1
0
1
0
1
CDH
(-1A)
0
1
0
1
73H
64
Manufacturer’s JEDEC ID code
1
0
FEH
Elpida Memory
65 to 71
Manufacturer’s JEDEC ID code
0
00H
72
Manufacturing location
73 to 90
Manufacturer’s part number
91 to 92
Revision code
93 to 94
Manufacturing date
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