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參數(shù)資料
| 型號(hào)： | EBD25RB4ALFB-7A |
| 英文描述： | SDRAM|DDR|32MX72|CMOS|DIMM|184PIN|PLASTIC |
| 中文描述： | 內(nèi)存|復(fù)員| 32MX72 |的CMOS |內(nèi)存| 184PIN |塑料 |
| 文件頁數(shù)： | 16/17頁 |
| 文件大小： | 158K |
| 代理商： | EBD25RB4ALFB-7A |
EBD25RB4ALFB
Data Sheet . E0236E10 (Ver. 1.0)
8
Differential Clock Net Wiring (CLK0, /CLK0)
120
240
(Typically two registers per DIMM)
0ns (nominal)
240
120
120
CLK0
Notes: 1. The clock delay from the input of the PLL clock to the input of any SDRAM or register willl
be set to 0ns (nominal).
2. Input, output and feedback clock lines are terminated from line to line as shown, and not
from line to ground.
3. Only one PLL output is shown per output type. Any additional PLL outputs will be wired
in a similar manner.
4. Termination resistors for feedback path clocks are located after the pins of the PLL.
C
/CLK0
SDRAM
stack
SDRAM
stack
Register1
Register2
PLL
Feedback
IN
OUT1
OUT'N'
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