參數(shù)資料
型號(hào)： E6420-EDGE6420
英文描述： Per-Pin Electronics Companion DAC
中文描述： 按針腳電子伴侶援
文件頁(yè)數(shù)： 5/29頁(yè)
文件大?。?/td> 244K
代理商： E6420-EDGE6420
13
2000 Semtech Corp.
www .semtech.com
HIGH-PERFORMANCE PRODUCTS – ATE
Edge6420
Circuit Description (continued)
Digital Outputs
SDO is a CMOS output, swinging rail to rail between
DVDD and DGND.
Chip Reset and Power Up
RESET* for the Edge6420 is active low.
When the Edge6420 first powers up, the latches will turn
on to the same state as though RESET* had been asserted.
When RESET* is brought low, the latches, and therefore
the DAC levels, will go to a known state that corresponds
to a specific DATA code. See the "Application Information"
section for an example of how this functionality works.
The known states are:
Care should be taken to ensure RESET* is invoked properly.
It is critical to ensure that if a RESET* is asserted after
UPDATE has transitioned from a high to low state, that
RESET* stay low, at least 2
s. To understand this
precaution, notice in Figure 1 that UPDATE is delayed in
order to enable individual DAC latches. If RESET* is not
brought low for sufficient time, an individual DAC update
will occur.
By simply forcing the RESET* pulse low for a minimum of
2
s, when a CK frequency of 50 MHz or less is used, the
6420 will clear properly to the known states shown above.
Power Supply Sequence
Power supplies should be asserted in the following order:
1. VEE
2. AVDD
3. DVDD
4. AVCC
To avoid latchup and ensure a predictable power up, the
above sequence should be followed.
Analog Scan Test Feature
Voltage Outputs
Each voltage output of the Edge6420 has high impedance
FET(s) connected from the outputs to a common analog
scan line.
The feature utilizes the normal address decoding, as shown
on page 8, as well as a "high" level on the TEST_MODE
pin (see truth table below).
To test an output, a DAC should be loaded as shown by
timing in Figure 3. The clock should be stopped after the
falling edge of CK24 after UPDATE is unasserted. At this
point, the SCAN_OUT pin, which is an analog output, will
reflect the voltage at the addressed DAC's output pin.
Note that the scan output is switched off when the parallel
load is selected (address 64). This prevents a parallel
connection of all the DAC outputs when the scan feature
is used.
Figure 5. Voltage Output Scan
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e
t
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t
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T
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AH
0
1
BH
0
1
CH
0
1
DH
0
1
EH
0
FH
0
1
E
D
O
M
_
T
S
E
TE
T
A
T
S
N
A
C
S
0f
f
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n
a
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1n
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n
a
c
S
Address
Decoder
TEST_MODE
SCAN_OUT
VOUT_CH0_1
VOUT_CH0_2
VOUT_CH0_3
NOTE: When address 64 is invoked (parallel load),
scan is disabled.
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