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參數(shù)資料
| 型號(hào)： | E6420-EDGE6420 |
| 英文描述： | Per-Pin Electronics Companion DAC |
| 中文描述： | 按針腳電子伴侶援 |
| 文件頁(yè)數(shù)： | 26/29頁(yè) |
| 文件大小： | 244K |
| 代理商： | E6420-EDGE6420 |
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6
2000 Semtech Corp.
www .semtech.com
HIGH-PERFORMANCE PRODUCTS – ATE
Edge6420
Circuit Description
Grouping of DACs
DACs are separated into 4 channels of 6 distinct functional
groups. Groups are defined by:
–
Type (voltage or current output)
–
Resolution (# of bits)
–
Output range
–
Output compliance.
Table 1 defines the DACs on a per channel basis:
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Table 1. DAC Grouping
Note 1:
The max DAC range is achieved through specific AVCC, AVEE, and Gain resistor settings. See the
equations in the "DAC Voltage Output Overview", "DAC Current Output Overview", and specifications for details.
Note 2:
–128 LSB is equivalent to –128 * LSB, where LSB = Range / 213. For max range case of 3.6 mA,
this offset would thus be: –56.26
A of offset current at Code 0.
Note 3:
Compliance specified in the table is at IOUT = 1.3mA. Maximum compliance is lower at higher currents.
Please refer to specifications for compliance at other output currents.
Chip Overview
The Edge6420 provides 64 output levels (44 voltage and
20 current). These outputs can easily be configured to
generate the specific analog voltage and current
requirements for 4 channels of ATE pin electronics
including:
–
3 level driver
–
Window comparator
–
Active load
–
Per pin PMU
without requiring any scaling or shifting via external
components.
The Edge6420 has the flexibility to be used in other
configurations for other applications.
Programming of the chip is done using a 4 bit digital
interface comprised of:
–
Serial Data In
–
Clock
–
Update
–
Chip Enable.
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