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| 型號(hào)： | DX-DI-PCI32-SL |
| 英文描述： | Peripheral Miscellaneous |
| 中文描述： | 周邊雜項(xiàng) |
| 文件頁(yè)數(shù)： | 4/5頁(yè) |
| 文件大?。?/td> | 150K |
| 代理商： | DX-DI-PCI32-SL |
Recommended Design Experience
The LogiCORE PCI Interface is preimplemented, allowing
engineering focus on the unique user application functions
of a PCI design. Regardless, PCI is a high-performance
design that is challenging to implement in any technology.
Therefore, previous experience with building high-perfor-
mance, pipelined FPGA designs using Xilinx implementa-
tion
software,
constraint
recommended. The challenge to implement a complete PCI
design including user application functions varies depend-
ing on configuration and functionality of your application.
Contact your local Xilinx representative for a closer review
and estimation for your specific requirements.
files,
and
guide
files
is
Timing Specifications
The maximum speed at which your user design is capable
of running can be affected by the size and quality of the
design. The following tables show the key timing parame-
ters for the LogiCORE PCI Interface.
Table 3
lists the Timing Parameters in the 66MHz Imple-
mentations and
Table 4
lists Timing Parameters in the
33MHz Implementations.
Table 2:
PCI Bus Commands
Table 3:
Timing Parameters, 66MHz Implementations
Table 4:
Timing Parameters, 33MHz Implementations
CBE [3:0]
Command
PCI
Initiator
Yes
Yes
Yes
Yes
Ignore
Ignore
Yes
Yes
Ignore
Ignore
Yes
Yes
Yes
No
Yes
No
PCI
Target
Yes
Ignore
Yes
Yes
Ignore
Ignore
Yes
Yes
Ignore
Ignore
Yes
Yes
Yes
Ignore
Yes
Yes
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
Reserved
Memory Read
Memory Write
Reserved
Reserved
Configuration Read
Configuration Write
Memory Read Multiple
Dual Address Cycle
Memory Read Line
Memory Write Invalidate
Symbol
T
cyc
T
high
T
low
T
val
Parameter
Min
15
1
6
6
2
2
Max
30
-
-
6
2
CLK Cycle Time
CLK High Time
CLK Low Time
CLK to Signal Valid Delay
(bussed signals)
CLK to Signal Valid Delay
(point to point signals)
Float to Active Delay
Active to Float Delay
Input Setup Time to CLK
(bussed signals)
Input Setup Time to CLK
(point to point signals)
Input Hold Time from CLK
Reset Active to Output Float
T
val
2
2
6
2
T
on
T
off
T
su
2
2
-
3
2,3
-
14
1
-
T
su
5
2,3
-
T
h
0
2,3
-
-
T
rstoff
40
Notes:
1. Controlled by timespec constraints, included in product.
2. Controlled by SelectIO configured for PCI66_3.
3. Controlled by guide file, included in product.
Symbol
T
cyc
T
high
T
low
T
val
Parameter
Min
30
1
11
11
2
2
Max
-
-
-
11
2
CLK Cycle Time
CLK High Time
CLK Low Time
CLK to Signal Valid Delay
(bussed signals)
CLK to Signal Valid Delay
(point to point signals)
Float to Active Delay
Active to Float Delay
Input Setup Time to CLK
(bussed signals)
Input Setup Time to CLK
(point to point signals)
Input Hold Time from CLK
Reset Active to Output Float
T
val
2
2
11
2
T
on
T
off
T
su
2
2
-
7
2
-
28
1
-
T
su
10
2
-
T
h
0
2
-
-
T
rstoff
40
Notes:
1. Controlled by timespec constraints, included in product.
2. Controlled by SelectIO configured for PCI33_3 or PCI33_5.
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