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| 型號(hào)： | DX-DI-PCI32-SL |
| 英文描述： | Peripheral Miscellaneous |
| 中文描述： | 周邊雜項(xiàng) |
| 文件頁(yè)數(shù)： | 3/5頁(yè) |
| 文件大?。?/td> | 150K |
| 代理商： | DX-DI-PCI32-SL |
LogiCORE PCI32 Interface v3.0
DS 206 (v1.2) July 19, 2002
Data Sheet, v3.0.100
1-800-255-77783
PCI I/O Interface Block
The I/O interface block handles the physical connection to
the PCI bus including all signaling, input and output syn-
chronization,
output
three-state
request-grant handshaking for bus mastering.
controls,
and
all
User Application
The LogiCORE PCI Interface provides a simple, gen-
eral-purpose interface for a wide range of applications.
PCI Configuration Space
This block provides the first 64 bytes of Type 0, version 2.3
Configuration Space Header, as shown in
Table 1
, to sup-
port software-driven “Plug-and-Play” initialization and con-
figuration. This includes information for Command, Status,
and three Base Address Registers (BARs).
The capability for extending configuration space has been
built into the user application interface. This capability,
including the ability to implement a capabilities pointer in
configuration space, allows the user to implement functions
such as power management and message signaled inter-
rupts in the user application.
Parity Generator/Checker
This block generates and checks even parity across the AD
bus, the CBE# lines, and the parity signals. It also reports
data parity errors via PERR# and address parity errors via
SERR#.
Initiator State Machine
This block controls the PCI interface initiator functions. The
states implemented are a subset of those defined in Appen-
dix B of the
PCI Local Bus Specification
. The initiator control
logic uses one-hot encoding for maximum performance.
Target State Machine
This block controls the PCI interface target functions. The
states implemented are a subset of those defined in Appen-
dix B of the
PCI Local Bus Specification
. The target control
logic uses one-hot encoding for maximum performance.
Table 1:
PCI Configuration Space Header
Interface Configuration
The LogiCORE PCI Interface can easily be configured to fit
unique system requirements by using the Xilinx Web-based
Configuration and Download tool or by changing the HDL
configuration file. The following customization options,
among many others, are supported by the interface and are
described in the product design guide.
Base Address Registers (number, size, and type)
Configuration Space Header ROM
Burst Transfer
The PCI bus derives its performance from its ability to sup-
port burst transfers. The performance of any PCI applica-
tion depends largely on the size of the burst transfer. Buffers
to support PCI burst transfer can efficiently be implemented
using on-chip RAM resources.
Supported PCI Commands
Table 2
illustrates the PCI bus commands supported by the
LogiCORE PCI Interface.
Bandwidth
The LogiCORE PCI Interface supports fully compliant zero
wait-state burst operations for both sourcing and receiving
data. This interface supports a sustained bandwidth of up to
528 MBytes/sec. The design can be configured to take
advantage of the ability of the LogiCORE PCI Interface to
do very long bursts.
The flexible user application interface, combined with sup-
port for many different PCI features, gives users a solution
that lends itself to use in many high-performance applica-
tions. The user is not locked into one DMA engine; hence,
an optimized design that fits a specific application can be
designed.
31
16 15
0
Device ID
Vendor ID
00h
Status
Command
04h
Class Code
Rev ID
08h
BIST
Header Type
Latency Tim-
er
Cache Line
Size
0Ch
Base Address Register 0 (BAR0)
10h
Base Address Register 1 (BAR1)
14h
Base Address Register 2 (BAR2)
18h
Base Address Register 3 (BAR3)
1Ch
Base Address Register 4 (BAR5)
20h
Base Address Register 5 (BAR5)
24h
Cardbus CIS Pointer
28h
Subsystem ID
Subsystem Vendor ID
2Ch
Expansion ROM Base Address
30h
Reserved
CapPtr
34h
Reserved
38h
Max Lat
Min Gnt
Int Pin
Int Line
3Ch
Reserved
40h-FFh
Note:
Shaded areas are not implemented and return zero.
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