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| 型號： | DO-DI-PCI64-IP |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 1/5頁 |
| 文件大?。?/td> | 150K |
| 代理商： | DO-DI-PCI64-IP |
DS 206 (v1.2) July 19, 2002
Data Sheet, v3.0.100
1-800-255-77781
2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at
http://www.xilinx.com/legal.htm
. All other
trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this fea-
ture, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may
require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warran-
ties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.
Introduction
With the Xilinx LogiCORE PCI Interface, a designer can
build a customized, fully PCI 2.3-compliant core with the
highest possible sustained performance, 528 Mbytes/sec.
Features
Fully PCI 2.3-compliant core, 64/32-bit, 66/33 MHz
interface
Customizable, programmable, single-chip solution
Predefined implementation for predictable timing
Incorporates Xilinx Smart-IP Technology
3.3 V operation at 0-66 MHz
5.0 V operation at 0-33 MHz
Fully verified design tested with Xilinx proprietary
testbench and hardware
Available for configuration and download on the web:
-
Web-based Configuration and Download Tool
-
Web-based User Constraint File Generator Tool
CardBus compliant
Supported initiator functions:
-
Configuration Read, Configuration Write
-
Memory Read, Memory Write, MRM, MRL
-
Interrupt Acknowledge, Special Cycles
-
I/O Read, I/O Write
Supported target functions:
-
Type 0 Configuration Space Header
-
Up to 3 Base Address Registers (MEM or I/O with
adjustable block size from 16 bytes to 2 Gbytes)
-
Medium Decode Speed
-
Parity Generation, Parity Error Detection
-
Configuration Read, Configuration Write
-
Memory Read, Memory Write, MRM, MRL
-
Interrupt Acknowledge
-
I/O Read, I/O Write
-
Target Abort, Target Retry, Target Disconnect
0
LogiCORE PCI32 Interface v3.0
DS 206 (v1.2) July 19, 2002
0
0
Data Sheet, v3.0.100
LogiCORE Facts
PCI64 Resource Utilization
1
Slice Four Input LUTs
Slice Flip Flops
IOB Flip Flops
IOBs
TBUFs
GCLKs
PCI32 Resource Utilization
1
Slice Four Input LUTs
Slice Flip Flops
IOB Flip Flops
IOBs
TBUFs
GCLKs
Provided with Core
Documentation
724
732
176
89
352
1
2
553
566
97
50
288
1
2
PCI Design Guide
PCI Implementation Guide
Verilog/VHDL Simulation Model
Design File Formats
NGO Netlist
Constraint Files
User Constraint Files (UCF)
Guide Files (NCD)
Verilog/VHDL Example Design
Design Tool Requirements
Example Design
Xilinx Tools
Tested Entry and
Verification Tools
3
v4.2i, Service Pack 3
Synplicity Synplify
Synopsys FPGA Express
Exemplar Leonardo Spectrum
Xilinx XST
4
Cadence Verilog XL
Model Technology ModelSim
1. The resource utilization depends on configuration of the interface and the user
design. Unused resources are trimmed by the Xilinx technology mapper. The utili-
zation figures reported in this table are representative of a maximum configuration.
2. Designs running at 66 MHz in devices other than Virtex-II require one GCLKIOB
and two GCLKs.
3. See the implementation guide or product release notes for current supported ver-
sions.
4. XST is command line option only. See Implementation Guide for details.
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| DO-DI-TPCDEC | 功能描述:LICENSE TURBO PROD CODE DECODER RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 軟件 系列:* 標(biāo)準(zhǔn)包裝:1 系列:ISE® 設(shè)計套件 類型:訂閱 適用于相關(guān)產(chǎn)品:Xilinx FPGAs 其它名稱:Q4986209T1081384 |
| DO-DI-TPCENC | 功能描述:LICENSE TURBO PROD CODE ENCODER RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 軟件 系列:* 標(biāo)準(zhǔn)包裝:1 系列:ISE® 設(shè)計套件 類型:訂閱 適用于相關(guān)產(chǎn)品:Xilinx FPGAs 其它名稱:Q4986209T1081384 |
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