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| 型號： | DX-DI-64IP-XVE |
| 英文描述： | Peripheral Miscellaneous |
| 中文描述： | 周邊雜項 |
| 文件頁數(shù)： | 4/5頁 |
| 文件大?。?/td> | 164K |
| 代理商： | DX-DI-64IP-XVE |
LogiCORE PCI Interface v3.0
4
www.xilinx.com
1-800-255-7778
DS 208 (v.1.2) June 28, 2002
Data Sheet, v3.0.99
Initiator State Machine
This block controls the PCI-X and PCI interface for initiator
functions. The initiator control logic also uses one-hot
encoding for maximum performance.
User Interface
The PCI-X interface provides a simplified user application
interface which allows a user to create one design that han-
dles both PCI-X and PCI transactions without design
changes, and both 32-bit and 64-bit data transfers without
external data width conversion. This eliminates the need for
multiple designs to support PCI-X and PCI and varying bus
widths.
This streamlined interface also simplifies the amount of
work needed to create a user application. The user inter-
face can be designed as either a 32-bit or 64-bit interface
and the PCI-X interface will automatically handle data con-
versions regardless of the width of the PCI-X or PCI bus.
Interface Configuration
The LogiCORE PCI-X Interface can easily be configured to
fit unique
system requirements by
Web-based Configuration and Download Tool or by chang-
ing the HDL configuration file. The following customization
options, among many others, are supported by the interface
and are described in the product design guide.
Base Address Registers (number, size, and mode)
Expansion ROM BAR
Cardbus CIS pointer
Configuration Space Header ROM
Interrupt Connectivity
Extended Command Use
Capability Configuration
using
the
Xilinx
Burst Transfer
The PCI-X bus derives its performance from its ability to
support burst transfers. The performance of any PCI-X
application depends largely on the size of the burst transfer.
Buffers to support PCI-X burst transfer can efficiently be
implemented using on-chip RAM resources.
Supported PCI Commands
Table 2
lists the PCI bus commands supported by the Logi-
CORE PCI-X Interface, and
Table 3
lists the supported
PCI-X bus commands.
Table 2:
PCI Bus Commands
Table 3:
PCI-X Bus Commands
Bandwidth
The LogiCORE PCI-X Interface supports fully compliant
zero wait-state burst operations for both sourcing and
receiving data. This interface supports a sustained band-
width of up to 800 MBytes/sec. The design can be config-
ured to take advantage of the ability of the LogiCORE PCI-X
Interface to do very long bursts.
The flexible user application interface, combined with sup-
port for many different PCI-X features, gives users a solu-
tion that lends itself to use in many high-performance
applications. The user is not locked into one DMA engine,
hence, an optimized design that fits a specific application
can be designed.
CBE [3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1. This command can only be used for a single dword transfer.
2. These commands have fixed byte enables of
0h
.
Command
Initiator
Yes
Yes
Yes
Yes
Ignore
Ignore
Yes
Yes
Ignore
Ignore
Yes
Yes
Yes
Yes
Yes
Yes
Target
Yes
No
Yes
Yes
Ignore
Ignore
Yes
Yes
Ignore
Ignore
Yes
Yes
Yes
Yes
Yes
Yes
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
Reserved
Memory Read
1
Memory Write
Reserved
Reserved
Configuration Read
Configuration Write
Memory Read Multiple
2
Dual Address Cycle
Memory Read Line
2
Memory Write Invalidate
2
CBE [3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Command
Initiator
Yes
Yes
Yes
Yes
Ignore
Ignore
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Target
Yes
No
Yes
Yes
Ignore
Ignore
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
Reserved
Memory Read Dword
Memory Write
Alias to Memory Read Block
Alias to Memory Write Block
Configuration Read
Configuration Write
Split Completion
Dual Address Cycle
Memory Read Block
Memory Write Block
相關(guān)PDF資料 |
PDF描述 |
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| DO-DI-PCIX64-VE | Peripheral Miscellaneous |
| DX-DI-PCI32-SL | Peripheral Miscellaneous |
| DO-DI-10GEMAC | Controller Miscellaneous - Datasheet Reference |
| DO-DI-PCI32-IP | Peripheral Miscellaneous |
| DO-DI-PCI32-SP | Peripheral Miscellaneous |
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