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參數(shù)資料
型號(hào)： DX-DI-64IP-XVE
英文描述： Peripheral Miscellaneous
中文描述： 周邊雜項(xiàng)
文件頁(yè)數(shù)： 3/5頁(yè)
文件大小： 164K
代理商： DX-DI-64IP-XVE
LogiCORE PCI Interface v3.0
DS 208 (v.1.2) June 28, 2002
Data Sheet, v3.0.99
1-800-255-7778
3
Decode
When an address is broadcast on the bus, the decode mod-
ule compares it to the base address registers for a match. If
one occurs, the target state machine is activated.
PCI-X Configuration Space
This block provides the first 64 bytes of Type 0, version 2.3
Configuration Space Header, and an additional 64 bytes
reserved for extended capabilities, as shown in
Table 1
. The
remaining 128 bytes of configuration space are available to
the user for application specific registers. Together, these
support software-driven “Plug-and Play” initialization and
configuration. This includes information for Command, Sta-
tus, Base Address Registers, and the extended capabilities
required for PCI-X.
Three extended capabilities are provided in the interface:
PCI-X Capability Item
Power Management Capability Item
Message Signalled Interrupt Capability Item
These capability items may be linked or delinked from the
capabilities list as required, and user functions can be inte-
grated into the capabilities list.
Table 1:
PCI-X Configuration Space Header
Watchdog
The watchdog monitors various system conditions, includ-
ing bus mode and bus width. This module also indicates if
run-time reconfiguration is required for loading different bit-
streams.
Target State Machine
This block controls the PCI-X and PCI interface for target
functions. The controller is a high-performance state
machine using one-hot encoding for maximum perfor-
mance.
Figure 1:
LogiCORE PCI-X Interface Block Diagram
data path mux
targ
init
Initiator Status
Initiator Control
Target Control
Target Status
Initiator Datapath Out
Initiator Datapath In
Target Datapath Out
Target Datapath In
Initiator
State
Machine
Target
State
Machine
Config
Space
Decode
Watchdog
data path mux
data path mux
data path mux
Target Hit
31
16 15
0
Device ID
Vendor ID
00h
Status
Command
04h
Class Code
Rev ID
08h
BIST
Header Type
Latency Tim-
er
Cache Line
Size
0Ch
Base Address Register 0 (BAR0)
10h
Base Address Register 1 (BAR1)
14h
Base Address Register 2 (BAR2)
18h
Base Address Register 3 (BAR3)
1Ch
Base Address Register 4 (BAR5)
20h
Base Address Register 5 (BAR5)
24h
Cardbus CIS Pointer
28h
Subsystem ID
Subsystem Vendor ID
2Ch
Expansion ROM Base Address
30h
Reserved
CapPtr
34h
Reserved
38h
Max Lat
Min Gnt
Interrupt Pin
Interrupt
Line
3Ch
Power Management Capa-
bility
NxtCap
PM Cap
40h
Data
PMCSR
BSE
PMCSR
44h
Message Control
NxtCap
MSI Cap
48h
Message Address
4Ch
Message Upper Address
50h
Reserved
Message Data
54h
PCI-X Command
NxtCap
PCI-X Cap
58h
PCI-X Status
5Ch
Reserved
60h-7Fh
Available User Configuration Space
80h-FFh
Note:
Shaded areas are not implemented and return zero.
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