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| 型號： | DX-DI-64IP-XVE |
| 英文描述： | Peripheral Miscellaneous |
| 中文描述： | 周邊雜項 |
| 文件頁數(shù)： | 2/5頁 |
| 文件大?。?/td> | 164K |
| 代理商： | DX-DI-64IP-XVE |
LogiCORE PCI Interface v3.0
2
1-800-255-7778Data Sheet, v3.0.99More Features
Supported PCI and PCI-X functions:
-
Memory Write
-
I/O Read
-
I/O Write
-
Configuration Read
-
Configuration Write
-
Interrupt Acknowledge
-
Bus Parking
-
Type 0 Configuration Space Header
-
Full 64-bit Addressing Support
-
Up to 6 Base Address Registers
-
Expansion ROM Base Address Register
-
Instant-On Base Address Registers
-
Parity Generation, Parity Error Detection
-
Full Command/Status Registers
Applications
Embedded applications in networking, industrial,
and telecommunication systems
PCI-X add-in boards such as frame buffers, network
adapters, and data acquisition boards
Hot swap CompactPCI-X boards
Any applications that need a PCI-X interface
General Description
The LogiCORE PCI-X Interface is a preimplemented and
fully tested module for Xilinx FPGAs. Critical paths are con-
trolled by constraint and guide files to ensure predictable
timing. This significantly reduces the engineering time
required to implement the PCI-X portion of your design.
Resources can instead be focused on your unique user
application logic in the FPGA and on the system level
design. As a result, LogiCORE PCI-X products minimize
your product development time.
The core meets the setup, hold, and clock to timing require-
ments as specified in the PCI-X specification. The interface
is verified through extensive simulation.
Other features that enable efficient implementation of a
PCI-X system include:
Block
SelectRAM
memory.
ultra-fast RAM with synchronous write and dual-port
RAM capabilities. Used in PCI-X designs to implement
FIFOs.
SelectRAM memory. Distributed on-chip ultra-fast RAM
with synchronous write option and dual-port RAM
capabilities. Used in PCI-X designs to implement
FIFOs.
Blocks
of
on-chip
The interface is carefully optimized for best possible perfor-
mance and utilization in Xilinx FPGA devices.
Smart-IP Technology
Drawing on the architectural advantages of Xilinx FPGAs,
Xilinx Smart-IP technology ensures the highest perfor-
mance, predictability, repeatability, and flexibility in PCI-X
designs. The Smart-IP technology is incorporated in every
LogiCORE PCI-X Interface.
Xilinx Smart-IP technology leverages the Xilinx architectural
advantages, such as look-up tables and segmented routing,
as well as floorplanning information, such as logic mapping
and location constraints. This technology provides the best
physical layout, predictability, and performance. Addition-
ally, these features allow for significantly reduced compile
times over competing architectures.
To guarantee the critical setup, hold, minimum clock to out,
and maximum clock to out timing, the PCI-X interface is
delivered with Smart-IP constraint files that are unique for a
device and package combination. These constraint files
guide the implementation tools so that the critical paths
always are within specification.
Xilinx provides Smart-IP constraint files for many device
and package combinations. Constraint files for unsupported
device and package combinations may be generated using
the web-based constraint file generator.
Functional Description
The LogiCORE PCI-X Interface is partitioned into six major
blocks and a user application as shown in
Figure 1
.
Datapath
There are four datapaths, in and out for both target and ini-
tiator. To improve timing and ease of design, the four unidi-
rectional datapaths are multiplexed inside the interface. All
data transfers are register-to-register. Since fewer registers
are on each datapath, loading is reduced and false timing
paths are eliminated.
LogiCORE Facts (Cont)
PCI-X 64 Supported Devices
Virtex-E V300EBG432-8C
Virtex-II 2V1000FG456-5C
Virtex-E V300EBG432-8C
Virtex-II 2V1000FG456-5C
PCI64/33
Only
PCI-X64/66
Only
PCI-X64/100
Only
PCI-X64/66
PCI64/33
Xilinx provides technical support for this LogiCORE product when used as described
in the Design Guide and the Implementation Guide. Xilinx cannot guarantee timing,
functionality, or support of product if implemented in devices not listed, or if custom-
ized beyond that allowed in the product documentation.
Note: Fully compliant designs over 66 MHz require two bitstreams.
Note: Universal card implementations not supported.
Note: Commercial devices only; 0 C < T
j
< 85 C.
3.3v only
3.3v only
3.3v only
3.3v only
Virtex-II 2V1000FG456-5C
3.3v only
Virtex-II 2V1000FG456-5C
3.3v only
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DO-DI-PCIX64-VE | Peripheral Miscellaneous |
| DX-DI-PCI32-SL | Peripheral Miscellaneous |
| DO-DI-10GEMAC | Controller Miscellaneous - Datasheet Reference |
| DO-DI-PCI32-IP | Peripheral Miscellaneous |
| DO-DI-PCI32-SP | Peripheral Miscellaneous |
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參數(shù)描述 |
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| DX-DI-PCI32-SL | 功能描述:LICENSE SOFTWARE UPGRADE RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 軟件 系列:* 標準包裝:1 系列:ISE® 設(shè)計套件 類型:訂閱 適用于相關(guān)產(chǎn)品:Xilinx FPGAs 其它名稱:Q4986209T1081384 |
| DX-DI-PCI64-IP | 功能描述:LICENSE SOFTWARE UPGRADE RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 軟件 系列:* 標準包裝:1 系列:ISE® 設(shè)計套件 類型:訂閱 適用于相關(guān)產(chǎn)品:Xilinx FPGAs 其它名稱:Q4986209T1081384 |
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