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參數(shù)資料
| 型號： | DT28F800F3T95 |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | FAST BOOT BLOCK FLASH MEMORY FAMILY 8 AND 16 MBIT |
| 中文描述： | 512K X 16 FLASH 2.7V PROM, 95 ns, PDSO56 |
| 封裝： | 16 X 23.70 MM, SSOP-56 |
| 文件頁數(shù)： | 37/47頁 |
| 文件大?。?/td> | 277K |
| 代理商： | DT28F800F3T95 |
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E
FAST BOOT BLOCK DATASHEET
37
PRODUCT PREVIEW
V
IH
V
IL
CLK (C)
Note 1
A
19-0
(A)
ADV# (V)
CE# (E)
OE# (G)
WE# (W)
V
IH
V
IL
V
OH
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
WAIT# (T)
V
OL
DQ
15-0
(D/Q)
V
OH
V
OL
Valid
Output
Valid
Output
Valid
Output
HValid
Output
Valid
Output
R7
R10
R10
Note 2
NOTE:
1.
This delay will only occur when burst length is configured as continuous. See Section 4.9.7 for further information about
the behavior of WAIT#.
WAIT# is configurable. It can be set to assert during or one CLK cycle before an output delay. See Section 4.9.4 for further
information.
2.
Figure 18. AC Waveform for Continuous Burst Read, Showing an Output Delay
with Data Output Configuration Set to One Clock
V
IH
V
IL
CLK (C)
Note 1
A
19-0
(A)
ADV# (V)
CE# (E)
OE# (G)
WE# (W)
V
IH
V
IL
V
OH
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
WAIT# (T)
V
OL
DQ
15-0
(D/Q)
V
OH
V
OL
Valid
Output
High Z
Valid
Output
R7
R10
Note 2
R10
NOTE:
1.
This delay will only occur when burst length is configured as continuous. See Section 4.9.7 for further infomation about
the behavior of WAIT#.
WAIT# is configurable. It can be set to assert during or one CLK cycle before an output delay. See Section 4.9.4 for further
information.
2.
Figure 19. AC Waveform for Continuous Burst Read, Showing an Output Delay
with Data Output Configuration Set to One Clock
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