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參數(shù)資料
| 型號(hào)： | DT28F800F3T95 |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | FAST BOOT BLOCK FLASH MEMORY FAMILY 8 AND 16 MBIT |
| 中文描述： | 512K X 16 FLASH 2.7V PROM, 95 ns, PDSO56 |
| 封裝： | 16 X 23.70 MM, SSOP-56 |
| 文件頁(yè)數(shù)： | 36/47頁(yè) |
| 文件大?。?/td> | 277K |
| 代理商： | DT28F800F3T95 |
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FAST BOOT BLOCK DATASHEET
E
36
PRODUCT PREVIEW
V
IH
V
IL
CLK (C)
Note 1
A
19-0
(A)
V
IH
V
IL
Valid
Address
R4
R18
R11
R9
R12
R16
R22
ADV# (V)
CE# (E)
V
IH
V
IL
V
IH
V
IL
R6
R5
OE# (G)
WE# (W)
V
IH
V
IL
V
OH
V
IH
V
IL
WAIT# (T)
V
OL
R20
R7
R8
R23
DQ
15-0
(D/Q)
V
OH
V
OL
Valid
Output
Valid
Output
Valid
Output
Valid
Output
High Z
R17
NOTE:
1.
Depending upon the frequency configuration code value in the read configuration register, insert clock cycles:
Frequency Configuration 2 insert two clock cycles
Frequency Configuration 3 insert three clock cycles
Frequency Configuration 4 insert four clock cycles
Frequency Configuration 5 insert five clock cycles
Frequency Configuration 6 insert six clock cycles
See Section 4.9.2 for further information about the frequency configuration and its effect on the initial read.
Figure 17. AC Waveform for Synchronous Burst Read Operations, Four Word Burst Length,
from Main Blocks
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