參數(shù)資料
型號: DSPIC30F2012-30I/SP
廠商: Microchip Technology
文件頁數(shù): 8/66頁
文件大?。?/td> 0K
描述: IC DSPIC MCU/DSP 12K 28DIP
產(chǎn)品培訓(xùn)模塊: Serial Communications using dsPIC30F I2C
Serial Communications using dsPIC30F SPI
Serial Communications using dsPIC30F UART
dsPIC30F 12 bit ADC - Part 2
dsPIC30F Addressing Modes - Part 1
dsPIC30F Architecture - Part 1
dsPIC30F DSP Engine & ALU
dsPIC30F Interrupts
dsPIC30F Motor Control PWM
dsPIC Timers
Asynchronous Stimulus
dsPIC30F Addressing Modes - Part 2
dsPIC30F Architecture - Part 2
dsPIC30F 12-bit ADC Part 1
標(biāo)準(zhǔn)包裝: 15
系列: dsPIC™ 30F
核心處理器: dsPIC
芯體尺寸: 16-位
速度: 30 MIP
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 20
程序存儲器容量: 12KB(4K x 24)
程序存儲器類型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 2.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-DIP(0.300",7.62mm)
包裝: 管件
產(chǎn)品目錄頁面: 650 (CN2011-ZH PDF)
配用: DV164005-ND - KIT ICD2 SIMPLE SUIT W/USB CABLE
其它名稱: DSPIC30F201230ISP
dsPIC30F
Flash
Programming
S
p
ecification
DS70102K-
page
16
2010
Microchip
T
echnolo
gy
Inc.
TABLE 5-8:
dsPIC30F CONFIGURATION REGISTERS (FOR dsPIC30F2010, dsPIC30F4011/4012 AND dsPIC30F6010/ 6011/6012/6013/
6014)
Address
Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0xF80000
FOSC
FCKSM<1:0>
FOS<1:0>
FPR<3:0>
0xF80002
FWDT
FWDTEN
FWPSA<1:0>
FWPSB<3:0>
0xF80004
FBORPOR
MCLREN
PWMPIN(1) HPOL(1)
LPOL(1)
BOREN
BORV<1:0>
FPWRT<1:0>
0xF80006
FBS
Reserved(2)
Reserved(2)
Reserved(2)
0xF80008
FSS
Reserved(2)
Reserved(2)
Reserved(2)
0xF8000A
FGS
Reserved(2)
GCP
GWRP
0xF8000C
FICD
BKBUG
COE
ICS<1:0>
Note
1:
On the 6011, 6012, 6013 and 6014, these bits are reserved (read as ‘1’ and must be programmed as ‘1’).
2:
Reserved bits read as ‘1’ and must be programmed as ‘1’.
TABLE 5-9:
dsPIC30F CONFIGURATION REGISTERS (FOR dsPIC30F5011/5013)
Address
Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0xF80000
FOSC
FCKSM<1:0>
FOS<1:0>
FPR<3:0>
0xF80002
FWDT
FWDTEN
FWPSA<1:0>
FWPSB<3:0>
0xF80004
FBORPOR
MCLREN
Reserved(1)
BOREN
BORV<1:0>
FPWRT<1:0>
0xF80006
FBS
RBS<1:0>
EBS
BSS<2:0>
0xF80008
FSS
RSS<1:0>
ESS<1:0>
SSS<2:0>
0xF8000A
FGS
GSS<1:0>
GWRP
0xF8000C
FICD
BKBUG
COE
ICS<1:0>
Note
1:
Reserved bits read as ‘1’ and must be programmed as ‘1’.
BWRP
SWRP
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