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| 型號： | DSPB56371AF150 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 33/68頁 |
| 文件大小： | 0K |
| 描述： | IC DSP 24BIT 150MHZ 80-LQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | DSP56K/Symphony |
| 類型： | 音頻處理器 |
| 接口： | 主機(jī)接口，I²C，SAI，SPI |
| 時鐘速率： | 150MHz |
| 非易失內(nèi)存： | ROM（384 kB） |
| 芯片上RAM： | 264kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.25V |
| 工作溫度： | -40°C ~ 115°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-LQFP |
| 供應(yīng)商設(shè)備封裝： | 80-LQFP（14x14） |
| 包裝： | 托盤 |
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Reset, Stop, Mode Select, and Interrupt Timing
DSP56371 Data Sheet, Rev. 4.1
Freescale Semiconductor
39
18
Delay from interrupt trigger to interrupt code
execution.
10 xTC + 5
60.0
ns
19
Duration of level sensitive IRQA assertion to
ensure interrupt service (when exiting Stop)2, 3
PLL is active during Stop and Stop delay is
enabled
(OMR Bit 6 = 0)
9+(128K
× TC)
704
—
us
PLL is active during Stop and Stop delay is not
enabled
(OMR Bit 6 = 1)
25
× TC
138
—
ns
PLL is not active during Stop and Stop delay is
enabled (OMR Bit 6 = 0)
9+(128KxTC)+Tlock
5.7
ms
PLL is not active during Stop and Stop delay is
not enabled (OMR Bit 6 = 1)
(25 x TC)+Tlock
5ms
20
Delay from IRQA, IRQB, IRQC, IRQD, NMI
assertion to general-purpose transfer output
valid caused by first interrupt instruction
execution
10 x TC + 3.0
59.0
ns
21
Interrupt Requests Rate
ESAI, ESAI_1, SHI, DAX, Timer
12 x TC
——
ns
DMA
8 x TC
——
ns
IRQ, NMI (edge trigger)
8 x TC
——
ns
IRQ (level trigger)
12 c TC
——
ns
22
DMA Requests Rate
Data read from ESAI, ESAI_1, SHI, DAX
6 x TC
——
ns
Data write to ESAI, ESAI_1, SHI, DAX
7 x TC
——
ns
Timer
2 x TC
——
ns
IRQ, NMI (edge trigger)
3 x TC
——
ns
Note:
1. When using fast interrupts and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply
to prevent multiple interrupt service. To avoid these timing restrictions, the deasserted Edge-triggered mode is
recommended when using fast interrupts. Long interrupts are recommended when using Level-sensitive mode.
2. For PLL disable, using external clock (PCTL Bit 13 = 0), no stabilization delay is required and recovery time will be
defined by the OMR Bit 6 settings.
For PLL enable, (if bit 12 of the PCTL register is 0), the PLL is shutdown during Stop. Recovering from Stop requires the
PLL to get locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 0.5 ms.
3. Periodically sampled and not 100% tested
4. RESET duration is measured during the time in which RESET is asserted, VDD is valid, and the EXTAL input is active and
valid. When the VDD is valid, but the other “required RESET duration” conditions (as specified above) have not been yet
met, the device circuitry will be in an uninitialized state that can result in significant power consumption and heat-up.
Designs should minimize this state to the shortest possible duration.
Table 19. Reset, Stop, Mode Select, and Interrupt Timing (continued)
No.
Characteristics
Expression
Min
Max
Unit
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