參數(shù)資料
型號(hào)： DSP56857BUE
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： 16-bit Digital Signal Controllers
中文描述： 16位數(shù)字信號(hào)控制器
文件頁(yè)數(shù)： 7/53頁(yè)
文件大小： 680K
代理商： DSP56857BUE
Introduction
56857 Technical Data, Rev. 6
Freescale Semiconductor
7
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56857 are organized into functional groups, as shown in
Table 2-1
and
as illustrated in
Figure 2-1
. In
Table 3-1
each table row describes the package pin and the signal or signals
present.
1. V
DD
= V
DD CORE,
V
SS
= V
SS CORE,
V
DDIO
= V
DD IO,
V
SSIO
= V
SS IO,
V
DDA
= V
DD ANA,
V
SSA
= V
SS ANA
2. MODE A, MODE B and MODE C can be used as GPIO after the bootstrap process has completed.
3. The following Host Interface signals are multiplexed: HRWB to HRD, HDS to HWR, HREQ to HTRQ and HACK to HRRQ.
Table 2-1 Functional Group Pin Allocations
Functional Group
Number of Pins
Power (V
DD,
V
DDIO, or
V
DDA
)
(8, 12, 1)
1
Ground (V
SS,
V
SSIO,
or V
SSA
)
(5, 12, 2)
1
PLL and Clock
3
Chip Select Logic used as dedicated GPIO
4
Interrupt and Program Control
7
2
Host Interface (HI)*
16
3
Enhanced Synchronous Serial Interface (ESSI0) Port*
6
Enhanced Synchronous Serial Interface (ESSI1) Port*
6
Serial Communications Interface (SCI0) Ports*
2
Serial Communications Interface (SCI1) Ports*
2
Serial Peripheral Interface (SPI) Port*
4
Quad Timer Module Port*
4
JTAG/Enhanced On-Chip Emulation (EOnCE)
6
*Alternately, GPIO pins
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