參數(shù)資料
型號: DSP56854FGE
廠商: Freescale Semiconductor
文件頁數(shù): 54/60頁
文件大?。?/td> 0K
描述: IC DSP 16BIT 120MHZ 128-LQFP
標準包裝: 72
系列: 568xx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 120MHz
連通性: EBI/EMI,SCI,SPI,SSI
外圍設(shè)備: DMA,POR,WDT
輸入/輸出數(shù): 41
程序存儲器容量: 32KB(16K x 16)
程序存儲器類型: SRAM
RAM 容量: 16K x 16
電壓 - 電源 (Vcc/Vdd): 1.62 V ~ 1.98 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 128-LQFP
包裝: 托盤
56854 Technical Data, Rev. 6
58
Freescale Semiconductor
Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance.
This is especially critical in systems with higher capacitive loads that could create higher transient currents
in the VDD and GND circuits.
All inputs must be terminated (i.e., not allowed to float) using CMOS levels.
Take special care to minimize noise levels on the VDDA and VSSA pins.
When using Wired-OR mode on the SPI or the IRQx pins, the user must provide an external pull-up device.
Designs that utilize the TRST pin for JTAG port or Enhance OnCE module functionality (such as
development or debugging systems) should allow a means to assert TRST whenever RESET is asserted, as
well as a means to assert TRST independently of RESET. Designs that do not require debugging
functionality, such as consumer products, should tie these pins together.
The internal POR (Power on Reset) will reset the part at power on with reset asserted or pulled high but
requires that TRST be asserted at power on.
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