參數(shù)資料
型號： DSP56854FGE
廠商： Freescale Semiconductor
文件頁數(shù)： 29/60頁
文件大?。?/td> 0K
描述： IC DSP 16BIT 120MHZ 128-LQFP
標(biāo)準(zhǔn)包裝： 72
系列： 568xx
核心處理器： 56800E
芯體尺寸： 16-位
速度： 120MHz
連通性： EBI/EMI，SCI，SPI，SSI
外圍設(shè)備： DMA，POR，WDT
輸入/輸出數(shù)： 41
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： SRAM
RAM 容量： 16K x 16
電壓 - 電源 (Vcc/Vdd)： 1.62 V ~ 1.98 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 128-LQFP
包裝： 托盤
Reset, Stop, Wait, Mode Select, and Interrupt Timing
56854 Technical Data, Rev. 6
Freescale Semiconductor
35
IRQA, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction execution
in the interrupt service routine
tIDM
18T
—
ns
tIDM -FAST
14T
—
IRQA, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine
tIG
18T
—
ns
tIG -FAST
14T
—
IRQA Low to First Valid Interrupt Vector Address Out
recovery from Wait State4
tIRI
22T
—
ns
tIRI -FAST
18T
—
Delay from IRQA Assertion (exiting Stop) to External
Data Memory5
tIW
1.5T
—
ns
Delay from IRQA Assertion (exiting Wait) to External
Data Memory
Fast6
Normal7
tIF
18T
22ET
—
ns
RSTO pulse width8
normal operation
internal reset mode
tRSTO
128ET
8ET
—
1.
In the formulas, T = clock cycle. For fop = 120MHz operation and fipb = 60MHz, T = 8.33ns.
2.
Parameters listed are guaranteed by design.
3.
At reset, the PLL is disabled and bypassed. The part is then put into Run mode and tclk assumes the period of the source
clock, txtal, textal or tosc.
4.
The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is
not the minimum required so that the IRQA interrupt is accepted.
5.
The interrupt instruction fetch is visible on the pins only in Mode 3.
6.
Fast stop mode:
Fast stop recovery applies when external clocking is in use (direct clocking to XTAL) or when fast stop mode recovery is
requested (OMR bit 6 is set to 1). In both cases the PLL and the master clock are unaffected by stop mode entry. Recovery takes
one less cycle and tclk will continue same value it had before stop mode was entered.
7.
Normal stop mode:
As a power saving feature, normal stop mode disables and bypasses the PLL. Stop mode will then shut down the master
clock, recovery will take an extra cycle (to restart the clock), and tclk will resume at the input clock source rate.
8.
ET = External Clock period, For an external crystal frequency of 8MHz, ET=125 ns.
Table 4-7 Reset, Stop, Wait, Mode Select, and Interrupt Timing1, 2
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz
Characteristic
Symbol
Min
Max
Unit
See Figure
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