________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Rev: 063008
20 of 375
6.
Block Diagrams
Figure 6-1. Simplified Logical Block Diagram
(MII MODE)
RXD[0:4]
RX_CLK
RX_CRS
RX_ERR
COL1
TX_CLK
TX_EN
TXD[0:4]
MDC
MDIO
TCLK1
TDATA1
TSYNC1
RCLK1
RDATA1
RSYNC1
ETHERNET
MAC1
μP Port
DDR SDRAM PORT
C
S
A
0-A10
D0-
D
7
WR
R
D
INT
SD_UDM
SD_LDM
SD_LDQS
SD_UDQS
SDC
S
SRA
S
SCA
S
SW
E
SBA[0:1]
SDA[0:12]
SDATA[0:15]
SD_CL
K
SD_CL
K
SDCLKE
N
JT
AG
Pin
s
ARBITER/
BUFFER MANAGER
4
x
GFP/HDLC
ENCAPSULATORS
TRANSMIT SERIAL
PORT 1
JTAG
CLAD
(MII MODE)
RXD[0:4]
RX_CLK
RX_CRS
RX_ERR
COL2
TX_CLK
TX_EN
TXD[0:4]
MDC
MDIO
ETHERNET
MAC2
(X16
2/82/42
)
SYSCLKI
BRDIGE/FIL
TER
SPI
QoS
PRIORITY
SCHE
DU
LIN
G
4x
VCAT/LCAS
Add/Drop
OAM Frames
4x
GFP/HDL
C
DECAPSULATORS
4
x
VCAT/LCAS
TRANSMIT SERIAL
PORT 2
TRANSMIT SERIAL
PORT 16
RECEIVE SERIAL
PORT 1
RECEIVE SERIAL
PORT 2
RECEIVE SERIAL
PORT 16
TVDAT
A
TVCL
K
TVSYNC
TVDEN
RVDAT
A
RVCL
K
RVSYNC
RVDE
N
VOICE PORT(W41/W11)
TCLK2
TDATA2
TSYNC2
TMCLK4
TDATA16
TMSYNC4
RCLK2
RDATA2
RSYNC2
RCLK16
RDATA16
RSYNC16
SPI_MOSI
SPI_MISO
SPI_CLK
CIR/CBS