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5.3
Ancillary Device Selection
All devices in the product family require an external DDR SDRAM for operation. The user must select a JEDEC
JESD79D compliant DDR SDRAM. DDR 266 or faster may be used. The recommended size is 256 Mbit (4 Meg x
16 x 4 banks), although it is possible to use other sizes (see Section
5.4). P2P operation is supported, and 0-ohm
series termination is possible with proper PCB layout.
All devices in the product family require an external microprocessor for configuration and status monitoring.
Because the DS33X162 family of devices are designed to require only a minimal amount of processor support, an
inexpensive microcontroller can normally be used. In applications which make extensive use of the support for
higher-layer protocols may require additional protocol processing capability, microprocessor selection can normally
be determined by evaluating the management frame processing requirements of the particular application. All
devices in the product family are designed to support both polled and interrupt-driven environments.
Microprocessor control is possible through the 8-bit parallel control port or SPI Slave port. More information on
microprocessor control is available in Section
8.1. Note that the parallel bus is not available in the 144 pin
DS33X11, and the SPI Slave port must be used for processor control.
Depending on the application, external PDH framers and LIUs may be required. Maxim offers a broad range of
framers, LIUs, and single-chip transceivers compatible with the DS33X162 family of products.
The Ethernet interface will normally be connected to an external Ethernet PHY or Ethernet switch device. Many
commercially-available products are available and will seamlessly interface with the device’s MII, RMII, or GMII
options.
Several external clock sources are required for proper operation. See Section
8.3 for more information.
5.4
Circuit Design
Note that all devices except the DS33X11, DS33W11, and DS33W41 share a common footprint. This is intended to
make it very easy to design a circuit that easily scales from 4 to 16 WAN ports with alternate assembly BOMs.
When designing a PCB for 4 or 8 ports, care should be taken to tie the unused input pins for serial ports 5-16 or 9-
16 to ground. This will allow for use of the higher density device for prototype purposes. Care should be taken that
outputs from the DS33X162 family device that are present in the high-port count option but not in the low port-count
option may potentially leave inputs on other devices floating, and should be pulled appropriately to a known
voltage.
The device’s DDR SDRAM interface is designed to use a JESD79D 256 Mbit (4 Meg x 16 x 4 bank) DDR SDRAM
with a 16 bit data bus. If a larger DDR SDRAM must be used, the lowest 13 address lines (A0-A12) should be
used, and care should be taken to ground any unused address inputs on the DDR SDRAM. Note that in such a
case, only 256 Mbits are addressable by the device. If a smaller JESD79D DDR SDRAM is to be used (such as the
128 Mbit MT46V8M16), the unused address outputs should be left unconnected, and care should be taken in
software to keep the starting and ending addresses of each queue within the same memory bank. In all cases, P2P
operation is supported, and 0
Ω series termination is possible with proper PCB layout.
5.5
Board Layout
The DDR SDRAM interface has particularly stringent layout requirements. Traces should have matched
impedances, be of equal length, and should not have stubs. Refer to the DDR SDRAM’s data sheet for more
information. Supply decoupling should be placed as close to the device as possible.
5.6
Software Development
All devices in the product family have a common register set. An example initialization sequence is shown in
Section
8.5. Software drivers and demonstration kit software are both available from Maxim. Go to