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參數(shù)資料
| 型號： | DS3234S#T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 5/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC W/TCXO 20-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 時鐘/日歷 |
| 特點： | 警報器，閏年，NVSRAM，方波輸出，TCXO/晶體 |
| 存儲容量： | 256B |
| 時間格式： | HH:MM:SS（12/24 小時） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | SPI |
| 電源電壓： | 2 V ~ 5.5 V |
| 電壓 - 電源，電池： | 2 V ~ 3.8 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SOIC W |
| 包裝： | 帶卷 (TR) |
DS3234
Alarms
The DS3234 contains two time-of-day/date alarms. Alarm
1 can be set by writing to registers 07h to 0Ah. Alarm 2
can be set by writing to registers 0Bh to 0Dh. The alarms
can be programmed (by the alarm enable and INTCN
bits of the control register) to activate the INT/SQW output
on an alarm match condition. Bit 7 of each of the time-of-
day/date alarm registers are mask bits (Table 2). When all
the mask bits for each alarm are logic 0, an alarm only
occurs when the values in the timekeeping registers
match the corresponding values stored in the time-of-
day/date alarm registers. The alarms can also be pro-
grammed to repeat every second, minute, hour, day, or
date. Table 2 shows the possible settings. Configurations
not listed in the table will result in illogical operations.
The DY/DT bits (bit 6 of the alarm day/date registers)
control whether the alarm value stored in bits 0 to 5 of
that register reflects the day of the week or the date of
the month. If DY/DT is written to logic 0, the alarm will
be the result of a match with date of the month. If
DY/DT is written to logic 1, the alarm will be the result of
a match with day of the week.
When the RTC register values match alarm register set-
tings, the corresponding Alarm Flag ‘A1F’ or ‘A2F’ bit is
set to logic 1. If the corresponding Alarm Interrupt
Enable ‘A1IE’ or ‘A2IE’ is also set to logic 1 and the
INTCN bit is set to logic 1, the alarm condition activates
the INT/SQW signal. The match is tested on the once-
per-second update of the time and date registers.
Table 2. Alarm Mask Bits
ALARM 1 REGISTER MASK BITS (BIT 7)
DY/DT
A1M4
A1M3
A1M2
A1M1
ALARM RATE
X
1
Alarm once per second
X
1
0
Alarm when seconds match
X
1
0
Alarm when minutes and seconds match
X
1
0
Alarm when hours, minutes, and seconds match
0
Alarm when date, hours, minutes, and seconds match
1
0
Alarm when day, hours, minutes, and seconds match
ALARM 2 REGISTER MASK BITS (BIT 7)
DY/DT
A2M4
A2M3
A2M2
ALARM RATE
X
1
Alarm once per minute (00 seconds of every minute)
X
1
0
Alarm when minutes match
X
1
0
Alarm when hours and minutes match
0
Alarm when date, hours, and minutes match
1
0
Alarm when day, hours, and minutes match
Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
____________________________________________________________________
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