參數資料
型號: DS3172N
英文描述: Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers
中文描述: 單/雙/三/四DS3/E3單芯片收發(fā)器
文件頁數: 87/232頁
文件大小: 2133K
代理商: DS3172N
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁當前第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁第231頁第232頁
DS3171/DS3172/DS3173/DS3174
87 of 231
The subframe alignment bits (F
X1
, F
X2
, F
X3
, and F
X4
) are overwritten with the values one, zero, zero, and one (1001)
respectively.
The X-bits (X
1
and X
2
) are both overwritten with the Remote Defect Indicator (RDI). The RDI source is
programmable (automatic, 1, or 0). If the RDI is generated automatically, the X-bits are set to zero when one or
more of the indicated alarm conditions is present, and set to one when all of the indicated alarm conditions are
absent. Automatically setting RDI on LOS, SEF, LOF, or AIS is individually programmable (on or off).
The P-bits (P
1
and P
2
) are both overwritten with the calculated payload parity from the previous DS3 frame. The
payload parity is calculated by performing modulo 2 addition of all of the payload bits after all frame processing has
been completed. P-bit generation is programmable (on or off). The P-bits will be generated if either P-bit generation
is enabled or frame generation is enabled.
If C-bit generation is enabled, the bit C
11
is overwritten with an alternating one zero pattern, and all of the other C-
bits (C
XY
) are overwritten with zeros. If C-bit generation is disabled, then all of the C-bit timeslots (C
XY
) will be
treated as payload data, and passed through. C-bit generation is programmable (on or off). Note: Overhead
insertion may still overwrite the C-bit time slots even if C-bit generation is disabled.
Once all of the DS3 overhead bits have been overwritten, the data stream is passed on to error insertion. If frame
generation is disabled, the incoming DS3 signal is passed on directly to error insertion. Frame generation is
programmable (on or off). Note: P-bit generation may still be performed even if frame generation is disabled.
10.6.6.3 Transmit M23 DS3 Error Insertion
Error insertion inserts various types of errors into the different DS3 overhead bits. The types of errors that can be
inserted are framing errors and P-bit parity errors.
The framing error insertion mode is programmable (F-bit, M-bit, SEF, or OOMF). An F-bit error is a single subframe
alignment bit (F
XY
) error. An M-bit error is a single multiframe alignment bit (M
1
, M
2
, or M
3
) error. An SEF error is an
error in all the subframe alignment bits in a subframe (F
X1
, F
X2
, F
X3
, and F
X4
). An OOMF error is a single multiframe
alignment bit (M
1
, M
2
, or M
3
) error in each of two consecutive DS3 frames.
A P-bit parity error is generated by is inverting the value of the P-bits (P
1
and P
2
) in a single DS3 frame. P-bit parity
error(s) can be inserted one error at a time, or continuously. The P-bit parity error insertion mode (single or
continuous) is programmable.
Each error type (framing or P-bit parity) has a separate enable. Continuous error insertion mode inserts errors at
every opportunity. Single error insertion mode inserts an error at the next opportunity when requested. The framing
multi-error insertion modes (SEF or OOMF) insert the indicated number of error(s) at the next opportunities when
requested; i.e., a single request will cause multiple errors to be inserts. The requests can be initiated by a register
bit(TSEI) or by the manual error insertion input (TMEI). The error insertion request source (register or input) is
programmable. The insertion of each particular error type is individually enabled. Once all error insertion has been
performed, the data stream is passed on to overhead insertion.
10.6.6.4 Transmit M23 DS3 Overhead Insertion
Overhead insertion can insert any (or all) of the DS3 overhead bits into the DS3 frame. The DS3 overhead bits X
1
,
X
2
, P
1
, P
2
, M
X
, F
XY
, and C
XY
can be sourced from the transmit overhead interface (TOHCLK, TOH, TOHEN, and
TOHSOF). The P-bits (P
1
and P
2
) are received as an error mask (modulo 2 addition of the input bit and the
internally generated bit). The DS3 overhead insertion is fully controlled by the transmit overhead interface. If the
transmit overhead data enable signal (TOHEN) is driven high, then the bit on the transmit overhead signal (TOH) is
inserted into the output data stream. Insertion of bits using the TOH signal overwrites internal overhead insertion.
10.6.6.5 Transmit M23 DS3 AIS/Idle Generation
M23 DS3 AIS/Idle generation overwrites the data stream with AIS or an Idle signal. If transmit Idle is enabled, the
data stream payload is forced to a 1100 pattern with two ones immediately following each DS3 overhead bit. M
1
,
M
2
, and M
3
bits are overwritten with the values zero, one, and zero (010) respectively. F
X1
, F
X2
, F
X3
, and F
X4
bits are
overwritten with the values one, zero, zero, and one (1001) respectively. X
1
and X
2
are overwritten with 11. P
1
and
P
2
are overwritten with the calculated payload parity from the previous output DS3 frame. And, C
31
, C
32
, and C
33
are overwritten with 000.
相關PDF資料
PDF描述
DS3173 Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers
DS3173N Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers
DS3174 Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers
DS3174N Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers
DS318PIN Industrial Control IC
相關代理商/技術參數
參數描述
DS3172N+ 功能描述:網絡控制器與處理器 IC Dual DS3/E3 Single Chip Transceiver RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3173 功能描述:網絡控制器與處理器 IC Triple DS3/E3 Single Chip Transceiver RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3173N 功能描述:網絡控制器與處理器 IC Triple DS3/E3 Single Chip Transceiver RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3174 功能描述:網絡控制器與處理器 IC Quad DS3/E3 Single Chip Transceiver RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3174+ 功能描述:網絡控制器與處理器 IC Quad DS3/E3 Single Chip Transceiver RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray