參數(shù)資料
型號： DS3148N
廠商： Maxim Integrated Products
文件頁數(shù)： 68/89頁
文件大?。?/td> 0K
描述： IC 8CH DS3/3 FRAMER 349-BGA
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1
控制器類型： DS3/E3 調(diào)幀器
接口： LIU
電源電壓： 3.135 V ~ 3.465 V
電流 - 電源： 640mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 349-BGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 349-HCBGA（27x27）
包裝： 托盤
DS3146/DS3146/DS31412 6-/8-/12-Channel DS3/E3 Framers
70 of 89
9. JTAG INFORMATION
The DS3146, DS3148, and DS31412 support the standard instruction codes SAMPLE/PRELOAD, BYPASS, and
EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. See the JTAG block diagram in
Figure 9-1. The device contains the following items, which meet the requirements set by the IEEE 1149.1 Standard
Test Access Port (TAP) and Boundary Scan Architecture:
Test Access Port (TAP)
TAP Controller
Instruction Register
Bypass Register
Boundary Scan Register
Device Identification Register
The Test Access Port has the necessary interface pins, namely JTCLK, JTDI, JTDO, and JTMS, and the optional
JTRST input. Details on these pins can be found in Section 5.6. Refer to IEEE 1149.1-1990, IEEE 1149.1a-1993,
and IEEE 1149.1b-1994 for details about the Boundary Scan Architecture and the Test Access Port.
Figure 9-1. JTAG Block Diagram
9.1 JTAG TAP Controller State Machine
This section covers the operation of the TAP controller state machine. See Figure 9-2 for details on each of the
states described below. The TAP controller is a finite state machine that responds to the logic level at JTMS on the
rising edge of JTCLK.
Test-Logic-Reset. When
JTRST is changed from low to high, the TAP controller starts in the Test-Logic-Reset
state, and the instruction register is loaded with the IDCODE instruction. All system logic and I/O pads on the
device operate normally.
Run-Test-Idle. Run-Test-Idle is used between scan operations or during specific tests. The instruction register and
test register remain idle.
BOUNDARY
SCAN
REGISTER
IDENTIFICATION
REGISTER
BYPASS
REGISTER
INSTRUCTION
REGISTER
TEST ACCESS PORT
CONTROLLER
MU
X
SELECT
TRI-STATE
JTDI
10k
W
JTMS
10k
W
JTCLK
JTRST
10k
W
JTDO
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