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參數(shù)資料
| 型號(hào)： | DS3148N |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 62/89頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 8CH DS3/3 FRAMER 349-BGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 控制器類型： | DS3/E3 調(diào)幀器 |
| 接口： | LIU |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 電流 - 電源： | 640mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 349-BGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 349-HCBGA（27x27） |
| 包裝： | 托盤 |
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DS3146/DS3146/DS31412 6-/8-/12-Channel DS3/E3 Framers
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Register Name:
FSRL
Register Description:
FEAC Status Register Latched
Register Address:
62h
Bit #
7
6
5
4
3
2
1
0
Name
N/A
RFFOL
RFFNL
RFIL
RFCDL
TFIL
Default
—
Note: See Figure 7-8 for details on the interrupt logic for the status bits in the BSRL register.
Bit 0: Transmit FEAC Idle Latched (TFIL). This latched status bit is set to 1 when the TFI status bit in the FSR
register goes high. TFIL is cleared when the host processor writes a 1 to it and is not set again until TFI goes high
again. When TFIL is set, it can cause a hardware interrupt to occur if the TFIIE bit in the FSRIE register and the
FEACIE bit in the MSRIE register are both set. The interrupt is cleared when this bit is cleared or one or both of the
interrupt-enable bits are cleared. This bit can be used to determine when the FEAC codeword transmission has
finished, and thus a new codeword can be transmitted.
Bit 1: Receive FEAC Codeword Detected Latched (RFCDL). This latched status bit is set to 1 when the RFCD
status bit in the FSR register goes high. RFCDL is cleared when the host processor writes a one to it and is not set
again until RFCD goes high again. When RFCDL is set, it can cause a hardware interrupt to occur if the RFCDIE
bit in the FSRIE register and the FEACIE bit in the MSRIE register are both set. The interrupt is cleared when this
bit is cleared or one or both of the interrupt-enable bits are cleared.
Bit 2: Receive FEAC Idle Latched (RFIL). This latched status bit is set to 1 when the RFI status bit in the FSR
register goes high. RFIL is cleared when the host processor writes a 1 to it and is not set again until RFI goes high
again. When RFIL is set, it can cause a hardware interrupt to occur if the RFIIE bit in the FSRIE register and the
FEACIE bit in the MSRIE register are both set. The interrupt is cleared when this bit is cleared or one or both of the
interrupt-enable bits are cleared. This bit can be used to determine when the FEAC receiver has stopped receiving
codewords, which can mark the end of an alarm situation.
Bit 3: Receive FEAC FIFO Not-Empty Latched (RFFNL). This latched status bit is set to 1 when the RFFE bit in
the FSR register goes low. RFFNL is cleared when the host processor writes a 1 to it and is not set again until the
RFFE bit goes low again. When RFFNL is set, it can cause a hardware interrupt to occur if the RFFNIE bit in the
FSRIE register and the FEACIE bit in the MSRIE register are both set. The interrupt is cleared when this bit is
cleared or one or both of the interrupt-enable bits are cleared. This bit can be used to determine when to read
FEAC codeword(s) from the FIFO.
Bit 4: Receive FEAC FIFO Overflow Latched (RFFOL). This latched status bit is set to 1 when the receive FEAC
controller has attempted to write to an already full receive FEAC FIFO and the current incoming FEAC codeword is
lost. RFFOL is cleared when the host processor writes a 1 to it and is not set again until another FIFO overflow
occurs (i.e., the receive FEAC FIFO has been read and then fills beyond capacity). When RFFOL is set, it can
cause a hardware interrupt to occur if the RFFOIE bit in the FSRIE register and the FEACIE bit in the MSRIE
register are both set. The interrupt is cleared when this bit is cleared or one or both of the interrupt-enable bits are
cleared.
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